VP536E View Datasheet(PDF) - Zarlink Semiconductor Inc
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VP536E Datasheet PDF : 14 Pages
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VP536E
The host pixel data can be phased relative to the active
video timing by counting the CLK12I clock periods from the
rising edge of HS. NTSC active video starts 48 CLK12I clock
cycles after the rising edge of the horizontal sync pulse
output, and PAL active video starts 58 CLK12I clock periods
after the rising edge of HS (HS and VS pulse edges coincide
with the rising edge of the CLK12I clock).
Input pixel data is ignored during the composite
blanking periods.
Color Space Matrix
The RGB color space is converted to a YUV color
space, using a transformation matrix defined by the NTSC
and PAL colorimetry definitions. If the input data format is
YUV, this block is bypassed without affecting the overall data
latency.
Interpolator
The luminance and chrominance data is separately
passed through interpolating filters to produce output
sampling rates double that of the incoming pixel rate. This
reduces the sinx/x distortion that is inherent in the digital to
analog converters and also simplifies the analog
reconstruction filter requirements.
Sinx/x Distortion Precompensation
The luminance data is precompensated for the sinx/x
distortion that is inherent in the digital to analog converters.
Since the chrominance data is contained within a relatively
narrow frequency range, it’s sinx/x distortion is compensated
for by increasing the gain of the chrominance DAC by a fixed
amount.
Digital To Analog Converters
The VP536E contains two 8-bit digital to analog
converters which produce the analog video signals. The
DACs use a current steering architecture in which bit
currents are routed to one of two outputs; thus each DAC
has a true and complimentary output. The use of identical
current sources and current steering their outputs means
that monotonicity is guaranteed. An on-chip voltage
reference of 1.0V (typ.) provides the necessary biasing.
However, the VP536E may be used in applications where an
external 1V reference is provided, in which case the external
reference should be temperature compensated and provide
a low impedance output.
The full-scale output currents of the DACs is set by
external resistors between the LUMAGAIN, CHROMAGAIN
and GND pins. An on-chip loop amplifier stabilizes the full-
scale output current against temperature and power supply
variations.
By summing the complimentary current outputs of the
two DACs, an inverted composite video signal is obtained.
Note that this signal has a DC offset. The analog outputs of
the VP536E are capable of directly driving a 37.5 ohm load,
such as a doubly terminated 75 ohm co-axial cable.
DAC Gain Adjust
The gains of the luma and chroma DACs are
independently adjustable. The gains are adjusted using the
external gain setting resistors between the LUMAGAIN,
CHROMAGAIN pins and GND.
For the correct DAC gains in the NTSC & PAL modes,
the LUMAGAIN resistance should be 837ohms. The
CHROMAGAIN resistance should be 520ohms for the
proper corresponding chroma amplitude (including sinx/x
compensation).
Luminance, Chrominance & Composite Video
Outputs
The Luminance video output (LUMAOUT pin) drives a
37.5 ohm load at 1.0V, sync tip to peak white. It contains only
the image’s luminance content plus the composite
synchronization pulses.
The chrominance video output (CHROMAOUT pin)
drives a 37.5 ohm load at levels proportional in amplitude to
the luma output. This output has a fixed offset current which
will produce approximately a 0.5V DC bias across the 37.5
ohm load. Burst is injected with appropriate timing relative to
the luma signal.
Luma, Chroma and true Composite video signals may
be obtained simultaneously through the use of an external
inverting video amplifier with the inverted composite video
output (COMPOUTB pin).
The inverted composite video output has a fixed DC
offset. Sync tip is the most positive voltage and is
approximately 1.5V with a 37.5 ohm load.
The NTSC and PAL output video waveforms of the
luma, chroma and inverted composite signals for 100%
amplitude, 100% saturated color bars are shown in Figs. 3-8.
Extendable S-Video Bandwidth
The bandwidth of color baseband signals is typically
limited in order to avoid modulation problems that develop in
composite video due to the interleaving of the chrominance
and luminance frequency components. The VP536E can use
either traditional bandwidth limited or extended bandwidth
baseband signals. For applications where the composite
signal is the main source of the video display, it is
recommended that bandwidth limiting be used in order to
reduce “dot-crawl” effects in the display. For S-Video
applications where the luma and chroma signals are
separate, enabling the extended bandwidth will result in
improved picture definition.
The enabling/disabling of this bandwidth extension is
controlled through the TCSPK pin as shown below.
Table 3: Bandwidth Control
TCSPK
Chroma Bandwidth
0
Extended Bandwidth
1
Limited Bandwidth
NOTE: TCSPK is internally pulled LOW, therefore
Extended Bandwidth is the default selection.
3
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