CDP1854A3 View Datasheet(PDF) - Intersil

Part Name

Description

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CDP1854A3

High Reliability CMOS Programmable Universal Asynchronous Receiver/Transmitter (UART)

Intersil 

CDP1854A/3, CDP1854AC/3

Dynamic Electrical Specifications tR, tF = 15ns, VIH = VDD, VIL = VSS, CL = 100pF, (See Figure 4)

PARAMETER

VDD

(V)

LIMITS

-55oC, +25oC

+125oC

MIN

MAX

MIN

MAX

CPU INTERFACE - READ TIMING - MODE 1

Pulse Width

TPB

tTT

5

125

-

165

-

10

70

-

80

-

Setup Time

RSEL to TPB

tRST

5

15

-

0

-

10

20

-

10

-

Hold Time

RSEL after TPB

tTRS

5

-10

-

-25

-

10

5

-

0

-

Propagation Delay Time

Read to Data Valid Time

tRDV

5

10

-

360

-

420

-

165

-

195

RESEL to Data Valid Time

tRSDV

5

10

-

250

-

295

-

125

-

145

UNITS

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

TPB

RSEL

R BUS 0-

R BUS 7

RD/WR, CS1, CS3

(NOTE 1)

tRST

tRSDV

tRDV

tTT

tTRS

CS2

NOTE:

1. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0.

FIGURE 4. MODE 1 CPU INTERFACE (READ) TIMING DIAGRAM

7

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