CDP1854A3 View Datasheet(PDF) - Intersil
Part Name
Description
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CDP1854A3 Datasheet PDF : 12 Pages
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CDP1854A/3, CDP1854AC/3
T CLOCK
tCC
tCH
tCL
tTHC
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
1 2 3 4 5 6 7 14 15 16 1 2 3
THRL
tTHTH
tCD
tCD
SDO
tTTHR
tCT
1ST DATA BIT
THRE
TSRE
T BUS 0
T BUS 7
tDT
tTD
DATA
tTTS
NOTES:
1. The holding register is loaded on the trailing edge of THRL.
2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + tTHC
after the trailing edge of THRL and transmission of a start bit occurs 1/2 clock period + tCD later.
FIGURE 6. MODE 0 TRANSMITTER TIMING DIAGRAM
tCC
tCH
tCL
CLOCK 7 1/2
SAMPLE
CLOCK 7 1/2 LOAD
HOLDING REGISTER
R CLOCK
tDC
(NOTE 1)
SDI
R BUS 0 -
R BUS 7
1 2 3 4 5 6 7 16 1 2 3 4 5 6 7 8 9
START BIT
PARITY
STOP BIT 1
tCDV
DATA
DA
DAR
OE
(NOTE 2)
PE
FE
tDDA
tDD
tCOE
tCPE
tCFE
tCDA
NOTES:
1. If a start bit occurs at a time less than tDC before a high-to-low transition of the clock, the start bit may not be recognized until the next
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding
register, the OE signal will come true.
FIGURE 7. MODE 0 RECEIVER TIMING DIAGRAM
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