CYIL2SM1300AA(2009) View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

View to exact match

CYIL2SM1300AA
(Rev.:2009)

LUPA 1300-2: High Speed CMOS Image Sensor

Cypress Semiconductor 

CYIL2SM1300AA

Programming the Exposure Time

In master mode, the exposure time is configured in two distinct methods (controlled by register seqmode3[6]):

■ #lines: Obvious, changing signals that control integration time. They are always changed during ROT to avoid any image artefacts.

■ #clock cycles: Must be multiplied by (2**seqmode4[3:0]). When the counter expires, changes are put into effect immediately. Asserting

the configuration signal (seqmode3[7]) forces delaying signal updates until the next ROT.

Table 15 lists the user programmable timer settings and how they are interpreted by the hardware.

Table 15. User Programmable Timer Settings

Setting

reg_res_length

reg_tint_timer

reg_tint_ds_timer

reg_tint_ts_timer

reg_rot_timer

reg_fot_timer

reg_sel_pre_timer

reg_precharge_timer

reg_sample_timer

reg_vmem_timer

reg_delayed_rdt_timer

Granularity

Lines/cycles

Lines/cycles

Lines/cycles

Lines/cycles

clock cycles

clock cycles

clock cycles

clock cycles

clock cycles

clock cycles

Lines/cycles

Note that the seqmode3[7] can also be used to sync the user signals in slave mode. The behavior is exactly the same.

Master Mode

In master mode the reset and exposure time is written in registers.

Figure 13. Integration and Image Readout in Master Mode

Ensure that the added value of the registers res_length and tint_timer always exceeds the number of lines that are read out. This is

because the sequencer samples a new image after integration is complete, without checking if image readout is finished. Enlarging

res_length to accommodate for this has no impact on image capture.

Document Number: 001-24599 Rev. *B

Page 19 of 41

[+] Feedback

Share Link: