CYIL2SM1300AA(2009) View Datasheet(PDF) - Cypress Semiconductor
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Description
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CYIL2SM1300AA Datasheet PDF : 41 Pages
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CYIL2SM1300AA
Table 14. Internal Registers (continued)
Block
Data Block
Register Name
Fix9
Fix10
dataconfig1
Address [6..0]
21
22
23
dataconfig2
24
Fix11
25
dacvrefadc
26
Fix12
27
Fix13
28
Fix14
29
datachannel0_1
30
datachannel0_2
31
datachannel1_1
32
Data Block
(continued)
datachannel1_2
33
Field
[7:0]
[7:0]
[1:0]
[2]
[3]
[4]
[5]
[7:6]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[0]
[1]
[2]
[3]
[5:4]
[7:0]
[0]
[1]
[2]
[3]
[5:4]
[7:0]
Reset Value
Description
0x20
Reserved, fixed value
0xC0
Reserved, fixed value
0x00
Reserved, fixed value
0
‘1’: Enables user upload of dacvrefadc register value
‘0’: Keeps default value
0
Enable PRBS generation
0
Reserved, fixed value
0
Reserved, fixed value
0x03
Training pattern inserted to sync LVDS receivers
0x2A
Training pattern inserted to sync LVDS receivers
0
Reserved, fixed value
0x80
Input to DAC to set the offset at the input of the ADC
0x80
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
0
Bypass the data block
0
Enables the FPN correction
0
Overwrite incoming ADC data by the data in the
testpat register
0
Reserved, fixed value
0x00
Pattern inserted to generate a test image
0x00
Pattern inserted to generate a test image
0
Bypass the data block
0
Enables the FPN correction
0
Overwrite incoming ADC data by the data in the
testpat register
0
Reserved, fixed value
0x00
Pattern inserted to generate a test image
0x00
Pattern inserted to generate a test image
datachannel12_1
54
datachannel12_2
55
[0] 0
[1] 0
[2] 0
[3] 0
[5:4] 0x00
[7:0] 0x00
Bypass the data block
Enables the FPN correction
Overwrite incoming ADC data by the data in the
testpat register
Reserved, fixed value
Pattern inserted to generate a test image
Pattern inserted to generate a test image
Document Number: 001-24599 Rev. *B
Page 12 of 41
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