CYIL2SM1300AA(2009) View Datasheet(PDF) - Cypress Semiconductor
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CYIL2SM1300AA Datasheet PDF : 41 Pages
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CYIL2SM1300AA
Image Sensor Timing and Readout
The timing of the sensor consists of two parts. The first part is
related to the exposure time and the control of the pixel. The
second part is related to the read out of the image sensor.
Integration and readout are in parallel or triggered. In the first
case, the integration time of frame I is ongoing during the readout
of frame I-1. Figure 11 shows this parallel timing structure.
The readout of every frame starts with a FOT, during which the
analog value on the pixel diode is transferred to the pixel memory
element. After this FOT, the sensor is read out line by line. The
read out of every line starts with a ROT, during which the pixel
value is put on the column lines. Then the pixels are selected in
groups of 24 (12 on rising edge, and 12 on the falling edge of the
internal clock). So in total, 54 kernels of 24 pixels are read out
every line. The internal timing is generated by the sequencer.
The sequencer can operate in two modes: master mode and
slave mode. In master mode, all internal timing is controlled by
the sequencer, based on the SPI settings. In slave mode, the
integration timing is directly controlled by over three pins, and the
readout timing is still controlled by the sequencer. The
seqmode1[1] register of the SPI selects between the master and
slave modes.
Figure 11. Global Readout Timing (Parallel)
Integration frame I+1
Integration frame I+2
FOT
Readout frame I
Readout Lines
L1
L2
...
Readout frame I+1
L1024
ROT
K1
K2
...
K54
Readout Pixels
Pipelined Shutter
Integration and readout occur in parallel and are continuous. You only need to start and stop the batch of image captures.
Integration of frame N is always ongoing during readout of frame N-1. The readout of every frame starts with a FOT, during which the
analog value on the pixel diode is transferred to the pixel memory element. After this FOT, the sensor is read out line by line. The
readout of every line starts with a ROT, during which the pixel value is put on the column lines. Then the pixels are muxed in the correct
ADCs, processed, and then sent to the LVDS output block.
Figure 12. Integration and Readout for Pipelined Shutter
Int. Time
Handling
Readout
Handling
Reset N Exposure Time N Reset
N+1
Exposure Time
FOT
Readout N-1
FOT
Readout N
ROT
Line Readout
You have two options in the pipelined shutter mode. The first option is to program the reset and integration through the configuration
interface and let the sequencer handle integration time automatically. This mode is called master mode. The second option is to drive
the integration time through an external pin. This mode is called slave mode.
Document Number: 001-24599 Rev. *B
Page 18 of 41
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