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M5M29FB800FP View Datasheet(PDF) - MITSUBISHI ELECTRIC

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M5M29FB800FP Datasheet PDF : 14 Pages
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MITSUBISHI LSIs
M5M29FB/T800FP,VP,RV-80,-10,-12
8,388,608-BIT (1048,576-WORD BY 8-BIT / 524,288-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITIONS
The device operations are selected by writing specific software
command into the Command User Interface.
Read Array Command (FFH)
The device is in Read Array mode on initial device powerup and
after exit from deep powerdown, or by writing FFH to the
Command User Interface. The device remains in Read Array
mode until the other commands are written.
Read Device Identifier Command (90H)
Though PROM programmers can normally read device identifier
codes by raising A9 to VID, multiplexing high voltage onto address
lines is not desired for micro-processor system. It is an other
means to read device identifier codes that Read Device Identifier
Code Command(90H) is written to the command latch. Following
the command write, the manufacturer code and the device code
can be read from address 0000H and 0001H, respectively.
Read Status Register Command (70H)
The Status Register is read after writing the Read Status Register
command of 70H to the Command User Interface.
The contents of Status Register are latched on the later falling
edge of /OE or /CE. So /CE or /OE must be toggled every status
read.
DATA PROTECTION
The M5M29FB/T800 provides selectable block locking of memory
blocks. Each block has an associated nonvolatile lock-bit which
determines the lock status of the block. In addition, the
M5M29FB/T800 has a master Write Protect pin (WP) which
prevents any modifications to memory blocks whose lock-bits are
set to "0", when /WP is low. When /WP is high or /RP is VHH, all
blocks can be programmed or erased regardless of the state of
the lock-bits, and the lock-bits are cleared to "1" by erase.
Power Supply Voltage
When the power supply voltage (Vcc) is less than 2.2V, the device
is set to the Read-only mode.
A delay time of 2 us is required before any device operation is
initiated. The delay time is measured from the time Vcc reaches
Vccmin (3.0V).
During power up, /RP=GND is recommended. Falling in Busy
status is not recommended for possibility of damaging the device.
Clear Status Register Command (50H)
The Erase Status and Program Status bits are set to "1"s by the
Write State Machine and can only be reset by the Clear Status
Register command of 50H. These bits indicates various failure
conditions.
Block Erase / Confirm Command (20H/D0H)
Automated block erase is initiated by writing the Block Erase
command of 20H followed by the Confirm command of D0H. An
address within the block to be erased is required. The WSM
executes iterative erase pulse application and erase verify
operation.
Page Program Commands(41H)
Page Program allows fast programming of 128words of data.
Writing of 41H initiates the page program operation. From 2nd
cycle to 129th cycle write data must be serially inputted. Address
A6-0 have to be incremented from 00H to 7FH. After completion
of data loading, the WSM controls the program pulse application
and verify operation.
Basically re-program must not be done on a page which has
already programmed.
Suspend/Resume Command (B0H/D0H)
Writing the Suspend command of B0H during block erase
operation interrupts the block erase operation and allows read out
from another block of memory. Writing the Suspend command of
B0H during program operation interrupts the program operation
and allows read out from another block of memory. The device
continues to output Status Register data when read, after the
Suspend command is written to it. Polling the WSM Status and
Suspend Status bits will determine when the erase operation or
program operation has been suspended. At this point, writing of
the Read Array command to the CUI enables reading data from
blocks other than that which is suspended. When the Resume
command of D0H is written to the CUI, the WSM will continue with
the erase or program processes.
3
May 1997 , Rev.6.1

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