EDS1232AATA-75MI View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

View to exact match

EDS1232AATA-75MI

128M bits SDRAM WTR (Wide Temperature Range)

Elpida Memory, Inc 

EDS1232AATA-MI

Current state

/CS /RAS /CAS /WE Address

Command

Operation

Notes

Write recovering H × × × ×

DESL

Nop → Enter row active after tDPL

L HHH×

NOP

Nop → Enter row active after tDPL

L HHL ×

BST

Nop → Enter row active after tDPL

L H L H BA, CA, A10 READ/READA Start read, Determine AP

8

L HL L

L L HH

L L HL

LLLH

LLLL

EWrite recovering H × × ×

with auto

L HHH

precharge

L HHL

OL H L H

L HL L

L L HH

LL L H L

BA, CA, A10

BA, RA

BA, A10

×

OPCODE

×

×

×

BA, CA, A10

BA, CA, A10

BA, RA

BA, A10

WRIT/ WRITA

ACT

PRE/PALL

REF/SELF

MRS

DESL

NOP

BST

READ/READA

WRIT/WRITA

ACT

PRE/PALL

New write, Determine AP

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

Nop → Enter precharge after tDPL

Nop → Enter precharge after tDPL

Nop → Enter row active after tDPL

ILLEGAL

ILLEGAL

ILLEGAL

ILLEGAL

3

3

3, 8

3

3

L L L H×

REF/SELF

ILLEGAL

Refresh

L L L L OPCODE

H× × × ×

MRS

DESL

ILLEGAL

Nop → Enter idle after tRC

L HHH×

NOP/BST

Nop → Enter idle after tRC

L HHL ×

READ/READA ILLEGAL

P L H L H ×

ACT/PRE/PALL ILLEGAL

L HL L ×

Mode register H × × × ×

REF/SELF/MRS ILLEGAL

DESL

Nop → Enter idle after tRSC

r accessing

L HHH×

NOP

Nop → Enter idle after tRSC

L HHL ×

BST

ILLEGAL

o L H L H ×

READ/READA ILLEGAL

d Remark:

LLLL×

ACT/PRE/PLL/ ILLEGAL

REF/SELF/MRS

H: VIH. L: VIL. ×: VIH or VIL, V = Valid data

BA: Bank Address, CA: Column Address, RA: Row Address

Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle.

2. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Power down

u mode.

3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),

depending on the state of that bank.

4. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Self refresh mode.

c All input buffers except CKE will be disabled.

5. Illegal if tRCD is not satisfied.

t 6. Illegal if tRAS is not satisfied.

7. Must satisfy burst interrupt condition.

8. Must satisfy bus contention, bus trun around, and/or write recovery requirements.

9. Must mask preceding data which don’t satisfy tDPL.

10. Illegal if tRRD is not satisfied.

Data Sheet E0340E30 (Ver. 3.0)

19

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