CYIL2SM1300AA(2009) View Datasheet(PDF) - Cypress Semiconductor
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CYIL2SM1300AA Datasheet PDF : 41 Pages
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CYIL2SM1300AA
The 6T Pixel
To obtain the global shutter feature combined with a high
sensitivity and good parasitic light sensitivity (PLS), implement
the pixel architecture shown in Figure 6. This pixel architecture
is designed in a 14 µm x 14 µm pixel pitch. The pixel is designed
to meet the specifications listed in Table 2 and Table 3 on page
2. This architecture also enables pipelined or triggered mode, as
shown in Figure 6.
Figure 6. 6T Pixel Architecture
Vpix
Vmem
Sample
Select
Reset
Frame Rate and Windowing
Frame Rate
The frame rate depends on the input clock, the frame overhead
time (FOT), and the row overhead time (ROT). The frame period
is calculated by:
Frame period = FOT+Nr. Lines * (ROT + Nr. Pixels * clock period)
Table 8. Frame Rate Parameters
Parameter
Comment
Clarification
FOT
Frame Overhead Programmable: Default
Time
315 MHz granularity clock
cycles (5 µs at 630 MHz)
ROT
Row Overhead
Time
Programmable: Default 13
granularity clock cycles
(206 ns at 630 MHz)
Nr. Lines
Number of lines
read out each
frame
Nr. Pixels
Number of pixels
read out each line
Clock Period 1/63 MHz = 15.9 ns Every channel works at
63 MHz Æ12 channels
result in 756 MHz data rate
Example
Readout of the full resolution at nominal speed (756 MHz pixel
rate = 1.32 ns)
Frame period = 5 µs + (1025 * (206 ns+1.32 ns*1296) = 1.97 ms
=> 507 fps
The real speed of the LUPA1300-2 is reduced to 500 fps,
because overhead pixels are read out for black level calibration
and other on board features.
Windowing
Windowing is easily achieved by SPI. The starting point of the x
and y address and the window size can be uploaded. The
minimum step size in the x-direction is 24 pixels (choose only
multiples of 24 as start or stop addresses). The minimum step
size in the y-direction is one line (every line can be addressed)
in normal mode, and two lines in sub sampling mode.
The section Sequencer on page 10 discusses the use of
registers to achieve the desired ROI.
Table 9. Typical Frame Rates for 630 MHz Clock
Image
Frame Rate Frame Read
Resolution (X*Y) (fps) Out Time (µs)
1296x1025
507
1970
640 x 512
1842
550
256 x 256
6933
146
Analog to Digital Converter
The sensor has 24 10-bit pipelined ADCs on board. The ADCs
nominally operate at 31.5 Msamples/s.
Table 10. ADC Parameters
Parameter
Data rate
Quantization
DNL
INL
Specification
31.5 Msamples/s
10 bit
Typ. < 1 DN
Typ. < 1 DN
Programmable Gain Amplifiers
The PGAs amplify the signal before sending it to the ADCs.
The amplification inside the PGA is controlled by one SPI setting:
afemode [5:3].
Six gain steps can be selected by the afemode<5:3> register.
Table 11 lists the six gain settings. The unity gain selection of the
PGA is done by the default afemode<5:3> setting.
Table 11. Gain Settings
afemode<5:3>
000
001
010
011
100
101
Gain
1
1.5
2
2.25
3
4
Document Number: 001-24599 Rev. *B
Page 8 of 41
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