CYIL2SM1300AA(2009) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
View to exact match
CYIL2SM1300AA Datasheet PDF : 41 Pages
| |||
CYIL2SM1300AA
Table 6. Power Dissipation [3]
These specifications apply for VDD = 2.5V, Clock = 315 MHz, 500 fps
Symbol
Parameter
Condition
PDOWN
Power
Power down
Average Power Dissipation
no clock running
lux = 0
Table 7. AC Electrical Characteristics [3]
The following specifications apply for VDD = 2.5V, Clock = 315 MHz, 500 fps.
Symbol
FCLK
DCCLK
fps
Parameter
Input Clock Frequency
Clock Duty Cycle
Frame rate
Condition
fps = 500
At maximum clock
Maximum clock speed
Typ
400
1350
Units
mW
mW
Typ
Max Units
315 MHz
50
%
500
fps
Sensor Architecture
The floor plan of the architecture is shown in Figure 5. The sensor consists of a pixel array, analog front end, data block, and LVDS
transmitters and receivers. Separate modules for the SPI, clock division, and sequencer are also integrated. The image sensor of
1280 x 1024 pixels is read out in progressive scan.
This architecture enables programmable addressing in the x-direction in steps of 24 pixels, and in the y-direction in steps of one pixel.
The starting point of the address can be uploaded by the serial parallel interface (SPI).
The AFE prepares the signal for the digital data block when the data is multiplexed and prepared for the LVDS interface.
Figure 5. Floor Plan of the Sensor
Image core
1280 x 1024
SPI
24 analog channels
31.5 Msps
Clk X & Clk Y
Analog front end
Sequencer
&
Logic
24x 10-bit digital channels
12x 10-bit digital channels
Local register
Data block
31.5 Msps
63 Msps
31.5 MHz
Clk in
Clock
Divider
Clk out
63 MHz
LVDS TX and RX
315 MHz
Document Number: 001-24599 Rev. *B
12x LVDS outputs at 630 Msps
Page 7 of 41
[+] Feedback
Share Link: 