PD45128163G5-A10LI-9JF View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

View to exact match

PD45128163G5-A10LI-9JF

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Elpida Memory, Inc 

µPD45128441-I, 45128841-I, 45128163-I

DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)

Parameter

Symbol

Test condition

/CAS Grade

latency

Maximum

×4

×8 ×16

Operating current

ICC1 Burst length = 1,

tRC ≥ tRC (MIN.), Io = 0 mA,

One bank active

CL = 2 -A75 100 100 110

-A80 100 100 110

-A10 100 100 110

CL = 3 -A75 105 105 115

Precharge standby current

in power down mode

Precharge standby current

in non power down mode

Active standby current

in power down mode

Active standby current

in non power down mode

Operating current

(Burst mode)

CBR (auto) refresh current

-A80 100 100 110

-A10 100 100 110

ICC2P CKE ≤ VIL (MAX.), tCK = 15 ns

1

1

1

ICC2PS CKE ≤ VIL (MAX.), tCK = ∞

1

1

1

ICC2N CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),

20

20

20

Input signals are changed one time during 30 ns.

ICC2NS CKE ≥ VIH (MIN.), tCK = ∞,

8

8

8

Input signals are stable.

ICC3P CKE ≤ VIL (MAX.), tCK = 15 ns

5

5

5

ICC3PS CKE ≤ VIL (MAX.), tCK = ∞

4

4

4

ICC3N CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),

30

30

30

Input signals are changed one time during 30 ns.

ICC3NS CKE ≥ VIH (MIN.), tCK = ∞ ,

20

20

20

Input signals are stable.

ICC4 tCK ≥ tCK (MIN.), Io = 0 mA,

CL = 2 -A75 105 120 145

All banks active

-A80 105 120 145

-A10 85

95

110

CL = 3 -A75 140 155 185

-A80 130 145 175

-A10 110 125 140

ICC5

tRC ≥ tRC (MIN.)

CL = 2 -A75 230 230 230

-A80 230 230 230

-A10 230 230 230

CL = 3 -A75 240 240 240

-A80 230 230 230

Self refresh current

ICC6 CKE ≤ 0.2 V

-A10 230 230 230

-**

2

2

2

-**L 0.8 0.8 0.8

Unit Notes

mA

1

mA

mA

mA

mA

mA

2

mA

3

mA

mA

Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In

addition to this, ICC1 is measured condition that addresses are changed only one time during tCK (MIN.).

2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In

addition to this, ICC4 is measured condition that addresses are changed only one time during tCK (MIN.).

3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).

Preliminary Data Sheet E0233N10

35

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