PD45128163G5-A10LI-9JF View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

View to exact match

PD45128163G5-A10LI-9JF

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Elpida Memory, Inc 

µPD45128441-I, 45128841-I, 45128163-I

12. Burst Termination

There are two methods to terminate a burst operation other than using a Read or a Write command. One is the

burst stop command and the other is the precharge command.

12.1 Burst Stop Command

During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus

goes to Hi-Z after the /CAS latency from the burst stop command.

Burst length = X

T0

T1

T2

T3

T4

T5

T6

T7

CLK

Command

/CAS latency = 2

DQ

/CAS latency = 3

DQ

READ

BST

Q1

Q2

Q3

Q1

Q2

Q3

Hi-Z

Hi-Z

Remark BST: Burst stop command

During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes

to Hi-Z at the same clock with the burst stop command.

Burst length = X

T0

T1

T2

T3

T4

T5

T6

T7

CLK

Command

WRITE

BST

/CAS latency = 2, 3

Hi-Z

DQ

D1

D2

D3

D4

Remark BST: Burst stop command

Preliminary Data Sheet E0233N10

31

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