SST89C54-33-I-PJ View Datasheet(PDF) - Silicon Storage Technology

Part Name

Description

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SST89C54-33-I-PJ

FlashFlex51 MCU

Silicon Storage Technology 

TABLE 3D: TIMER/COUNTERS SFRS

TMOD Timer/Counter

89h

Mode Control

TCON* Timer/Counter

88h

Control

TH0 Timer 0 MSB

8Ch

TL0

Timer 0 LSB

8Ah

TH1 Timer 1 MSB

8Dh

TL1

Timer 1 LSB

8Bh

T2CON* Timer / Counter 2

C8h

Control

TH2 Timer 2 MSB

CDh

TL2

Timer 2 LSB

CCh

RCAP2H Timer 2 Capture MSB CBh

RCAP2L Timer 2 Capture LSB CAh

* = Bit Addressable SFRs

FlashFlex51 MCU

SST89C54 / SST89C58

Preliminary Specifications

Timer 1

Timer 0

00h

GATE C/T# M1

M0 GATE C/T# M1 M0

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

00h

TH0[7:0]

00h

TL0[7:0]

00h

TH1[7:0]

00h

TL1[7:0]

00h

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# 00h

TH2[7:0]

TL2[7:0]

RCAP2H[7:0]

RCAP2L[7:0]

00h

00h

00h

00h

344 PGM T3D.0

TABLE 3E: INTERFACE SFRS

SBUF Serial Data Buffer

99h

SBUF[7:0]

Indeterminate

SCON* Serial Port Control 98h SM0 SM1 SM2 REN TB8 RB8 T1 R1

00h

P0*

Port 0

80h

P0[7:0]

FFh

P1*

Port 1

90h

-

-

-

-

-

T2 EX T2

FFh

P2*

Port 2

A0h

P2[7:0]

FFh

P3*

Port 3

B0h RD# WR# T1

T0 INT1# INT0# TXD0 RXD0 FFh

* = Bit Addressable SFRs

344 PGM T3E.3

FLASH MEMORY PROGRAMMING

The SST89C54/58 internal flash memory can be pro-

grammed or erased using the following two methods:

• External Host Mode (parallel only)

• In-Application Programming (IAP) Mode

(parallel or serial)

EXTERNAL HOST PROGRAMMING MODE

External Host Programming Mode provides the user with

direct Flash memory access to program the Flash

memory without using the CPU. External Host Mode is

entered by forcing PSEN# from a logic high to a logic low

while RST input is being held continuously high. The

SST89C54/58 will stay in External Host Mode as long as

RST = 1 and PSEN# = 0.

A READ-ID operation is necessary to “arm” the device,

no other External Host Mode command can be enabled

until a READ-ID is performed. In External Host Mode, the

internal Flash memory blocks are accessed through the

re-assigned I/O port pins (see Figure 9 for details) by an

external host, such as an MCU programmer, PCB tester

or a PC controlled development board.

© 2000 Silicon Storage Technology, Inc.

18

344-2 8/00

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