SST89C54-33-I-PJ View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
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SST89C54-33-I-PJ Datasheet PDF : 50 Pages
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FlashFlex51 MCU
SST89C54 / SST89C58
Preliminary Specifications
SuperFlash Configuration Register (SFCF)
Location
7
6
5
4
3
2
1
0 Reset Value
0B1h
VIS
IAPEN
–
–
–
–
MAP_EN1 MAP_EN0 000000xxb
1
Symbol
Function
2
VIS
Upper flash block visibility.
1: 4 KByte flash block visible from F000-FFFF.
0: 4 KByte flash block not visible.
3
IAPEN
Enable IAP operation.
1: IAP commands are enabled.
0: IAP commands are disabled.
4
MAP_EN1 Map enable bit 1.
MAP_EN0
Map enable bit 0.
MAP_EN[1:0] are initialized to default value according to Re-map [1:0] during Reset.
5
Refer to Table 2.
6
SuperFlash Command Register (SFCM)
Location
7
6
5
4
3
2
1
0
Reset Value
7
0B2h
FIE
FCM6 FCM5 FCM4 FCM3 FCM2 FCM1 FCM0 00000000b
8
Symbol
Function
FIE
Flash Interrupt Enable.
1: INT1# is re-assigned to signal IAP operation completion.
External INT1# interrupts are ignored.
9
0: INT1# is not reassigned.
FCM[6:0]
Flash operation command.
10
000_0001b Chip-Erase.
000_0110b Burst-Program.
000_1011b Sector-Erase.
000_1100b Byte-Verify. (1)
11
000_1101b Block-Erase.
000_1110b Byte-Program.
All other combinations are not implemented, and reserved for future use.
12
(1) Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE.
13
14
15
16
© 2000 Silicon Storage Technology, Inc.
15
344-2 8/00
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