ADUC812(1999) View Datasheet(PDF) - Analog Devices
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Description
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ADUC812 Datasheet PDF : 31 Pages
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ADuC812
PIN FUNCTION DESCRIPTIONS
Mnemonic Type Function
DVDD
P
AVDD
P
CREF
I
VREF
I/O
AGND
G
P1.0–P1.7
I
ADC0–ADC7 I
T2
I
T2EX
I
SS
I
SDATA
I/O
SCLOCK
I/O
MOSI
I/O
MISO
I/O
DAC0
O
DAC1
O
RESET
I
P3.0–P3.7
I/O
RxD
I/O
TxD
O
INT0
I
INT1
I
T0
I
T1
I
CONVST
I
WR
O
RD
O
XTAL2
O
XTAL1
I
DGND
G
P2.0–P2.7
I/O
(A8–A15)
(A16–A23)
PSEN
O
Digital Positive Supply Voltage, +3 V or +5 V nominal.
Analog Positive Supply Voltage, +3 V or +5 V nominal.
Decoupling pin for on-chip reference. Connect 0.1 µF between this pin and AGND.
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this
appears at the pin (once the ADC or DAC peripherals are enabled). This pin can be overdriven by an exter-
nal reference.
Analog Ground. Ground Reference point for the analog circuitry.
Port 1 is an 8-bit Input Port only. Unlike other Ports, Port 1 defaults to Analog Input Mode, to configure
any of these Port Pins as a digital input, write a “0” to the port bit. Port 1 pins are multifunction and share
the following functionality.
Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR.
Timer 2 Digital Input. Input to Timer/Counter 2. When Enabled, Counter 2 is incremented in response to
a 1 to 0 transition of the T2 input.
Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for
Counter 2.
Slave Select input for the SPI interface.
User selectable, I2C-Compatible Input/Output pin or SPI Data Input/Output pin.
Serial Clock pin for I2C-Compatible or SPI serial interface clock.
SPI Master Output/Slave Input Data I/O pin for SPI interface.
Master Input/Slave Output Data I/O pin for SPI Serial Interface.
Voltage Output from DAC0.
Voltage Output from DAC1.
Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the
device.
Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 3
pins being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also
contain various secondary functions which are described below.
Receiver Data Input (asynchronous) or Data Input/ Output (synchronous) of serial (UART) port.
Transmitter Data Output (asynchronous) or Clock Output (synchronous) of serial (UART) port.
Interrupt 0, programmable edge or level triggered Interrupt input, which can be programmed to one of two
priority levels. This pin can also be used as a gate control input to Timer 0.
Interrupt 1, programmable edge or level triggered Interrupt input, which can be programmed to one of two
priority levels. This pin can also be used as a gate control input to Timer 1.
Timer/Counter 0 Input.
Timer/Counter 1 Input.
Active low Convert Start Logic input for the ADC block when the external Convert start function is en-
abled. A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion.
Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.
Read Control Signal, Logic Output. Enables the external data memory to Port 0.
Output of the inverting oscillator amplifier.
Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
Digital Ground. Ground reference point for the digital circuitry.
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 2
pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits
the high order address bytes during fetches from external program memory and middle and high order
address bytes during accesses to the external 24-bit external data memory space.
Program Store Enable, Logic Output. This output is a control signal that enables the external program
memory to the bus during external fetch operations. It is active every six oscillator periods except during
external data memory accesses. This pin remains high during internal program execution. PSEN can also be
used to enable serial download mode when pulled low through a resistor on power-up or RESET.
–6–
REV. 0
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