ADUC812(1999) View Datasheet(PDF) - Analog Devices
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ADUC812 Datasheet PDF : 31 Pages
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ADuC812
ADCCON2 – (ADC Control SFR #2)
The ADCCON2 register controls ADC channel selection and
conversion modes as detailed below.
SFR Address:
D8H
SFR Power On Default Value: 00H
Bit Addressable:
YES
ADCI DMA CCONV SCONV CS3 CS2 CS1 CS0
Table II. ADCCON2 SFR Bit Designations
Bit
Location
Bit
Mnemonic Description
ADCCON2.7 ADCI
ADCCON2.6 DMA
ADCCON2.5 CCONV
ADCCON2.4 SCONV
ADCCON2.3 CS3
ADCCON2.2 CS2
ADCCON2.1 CS1
ADCCON2.0 CS0
The ADC interrupt bit (ADCI) is
set by hardware at the end of a
single ADC conversion cycle or at
the end of a DMA block conver-
sion. ADCI is cleared by hardware
when the PC vectors to the ADC
Interrupt Service Routine.
The DMA mode enable bit (DMA)
is set by the user to initiate a pre-
configured ADC DMA mode opera-
tion. A more detailed description of
this mode is given below.
The continuous conversion bit
(CCONV) is set by the user to
initiate the ADC into a continuous
mode of conversion. In this mode
the ADC starts converting based on
the timing and channel configura-
tion already set up in the ADCCON
SFRs, the ADC automatically starts
an other conversion once a previous
conversion cycle has completed.
The single conversion bit
(SCONV) is set by the user to
initiate a single conversion cycle.
The SCONV bit is automatically
reset to “0” on completion of the
single conversion cycle.
The channel selection bits (CS3-0)
allow the user to program the
ADC channel selection under
software control. Once a conver-
sion is initiated the channel
converted will be that pointed to
by these channel selection bits. In
DMA mode the channel selection
is derived from the channel ID
written to the external memory.
CS3 CS2 CS1 CS0 CH#
00000
00011
00102
00113
01004
01015
01106
01117
1 0 0 0 Temp Sensor
1 X X X Other
Combinations
1 1 1 1 DMA STOP
ADCCON3 – (ADC Control SFR #3)
The ADCCON3 register gives user software an indication of
ADC busy status.
SFR Address:
F5H
SFR Power On Default Value: 00H
Bit Addressable:
NO
BUSY RSVD RSVD RSVD CTYP CAL1 CAL0 CALST
Table III. ADCCON3 SFR Bit Designations
Bit
Location
Bit
Mnemonic Description
ADCCON3.7 BUSY
ADCCON3.6
ADCCON3.5
ADCCON3.4
ADCCON3.3
ADCCON3.2
ADCCON3.1
ADCCON3.0
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
The ADC busy status bit (BUSY)
is a read-only status bit that is set
during a valid ADC conversion or
calibration cycle. Busy is auto-
matically cleared by the core at the
end of conversion or calibration.
ADCCON3.0–3.6 are reserved
(RSVD) for internal use. These
bits will read as zero and should
only be written as zero by user
software.
ADC Internal Reference
If the internal reference is being used, both the VREF and CREF
pins should be decoupled with 100 nF capacitors to AGND.
These decoupling capacitors should be placed very close to the
VREF and CREF pins. For specified performance, it is recom-
mended that when using an external reference, this reference
should be between 2.3 V and the analog supply AVDD.
If the internal reference is required for use external to the
MicroConverter, it should be buffered at the VREF pin and a
100 nF capacitor should be connected from this pin to AGND.
The internal 2.5 V is factory calibrated to an absolute accuracy
of 2.5 V ± 50 mV. It should also be noted that the internal VREF
will remain powered down until either of the DACs or the ADC
peripheral blocks are powered on by their respective enable bits.
Calibration
The ADC block also has four associated calibration SFRs.
These SFR’s drive calibration logic ensuring optimum perfor-
mance from the 12-bit ADC at all times. As part of the power-
on reset configuration, these SFRs are configured automatically
and transparently from factory programmed calibration con-
stants. In many applications use of factory programmed calibra-
tion constants will suffice; however, these calibration SFRs may
be overwritten by user code to further compensate for system-
dependent offset and gain errors.
Calibration Overview
The ADC block incorporates calibration hardware that ensures
optimum performance from the ADC at all times. The calibra-
tion modes are exercised as part of the ADuC812 internal factory
final test routines. The factory calibration results are stored in
Flash memory and are automatically downloaded on any power-
on-reset event to initialize the ADC calibration registers. In
–10–
REV. 0
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