WM8581(2005) View Datasheet(PDF) - Wolfson Microelectronics plc

Part Name

Description

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WM8581
(Rev.:2005)

Multichannel CODEC with S/PDIF Transceiver

Wolfson Microelectronics plc 

WM8581

Production Data

DEVICE DESCRIPTION

INTRODUCTION

WM8581 is a complete mutli-channel CODEC with integrated S/PDIF transceiver. The device

comprises four separate stereo DACs and a stereo ADC, in a single package, and controlled by

either software or hardware interfaces.

The four stereo DAC outputs are ideal to implement a complete 7.1 channel surround system. Each

DAC has its own digital volume control (adjustable in 0.5dB steps) with zero cross detection. With

zero cross enabled, volume updates occur as a signal transitions through its zero point. This

minimises audible clicks and ‘zipper’ noise as the gain values change.

Each stereo DAC has its own data input (DIN1/2/3/4) and shared word clock (PAIFRX_LRCLK), bit

clock (PAIFRX_BCLK) and master clock (MCLK). The stereo ADC has data output (DOUT), word

clock (PAIFTX_LRCLK), and bit clock (PAIFTX_BCLK). This allows the ADC to operate at a different

sample rate to the DACs. In addition, a separate ADC master clock (ADCMCLK) can be used instead

of MCLK for further flexibility.

There are two independent Digital Audio Interfaces, which may be configured to operate in either

master or slave mode. In Slave mode, the LRCLKs and BCLKs are inputs. In Master mode, the

LRCLKs and BCLKs are outputs.

The Audio Interfaces support Right Justified, Left Justified, I2S and DSP formats. Word lengths of 16,

20, 24 and 32 bits are available (with the exception of 32 bit Right Justified).

Operation using system clocks of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs is provided. In

Slave mode, selection between clock rates is automatically controlled. In master mode, the master

clock to sample rate ratio is set by register control. Sample rates (fs) from less than 8ks/s up to

192ks/s are permitted providing the appropriate system clock is input.

The S/PDIF Transceiver is IEC-60958-3 compatible with 32k frames/s to 96k frames/s support.

S/PDIF data can be input on one of four pins, and routed internally to the Audio Interfaces, DAC1,

and S/PDIF transmitter. Error flags and status information can be read back over the serial interface,

or output on GPO pins. The S/PDIF Transmitter can source data from the ADC, S/PDIF Receiver or

Audio Interfaces. The Transceiver supports Consumer Mode Channel information, and transmitted

Channel bits can be configured via register control.

The Digital Routing paths between all the interfaces can be configured by the user, as can the

corresponding interface clocking schemes.

There are two PLLs, which can be independently configured to generate two system clocks for

internal or external use.

The serial control interface is controlled by pins CSB, SCLK, and SDIN, which are 5V tolerant with

TTL input thresholds, allowing the WM8581 to be used with DVDD = 3.3V and be controlled by a

controller with 5V output.

The WM8581 may also be controlled in hardware mode, selected by the HWMODE pin. In hardware

mode, limited control of internal functionality is available via the Multi-Function Pins (MFPs) and CSB,

SCLK, SDIN and MUTE pins.

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PD Rev 4.0 April 2007

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