WM8581(2005) View Datasheet(PDF) - Wolfson Microelectronics plc
Part Name
Description
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WM8581 Datasheet PDF : 100 Pages
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WM8581
CONTROL INTERFACE TIMING – 3-WIRE MODE
t
CSS
CSB
SCLK
t
SCY
Production Data
t
CSH
t
SCS
t
CSS
SDIN
SDO
t
DSU
t
DHO
t
DL
Figure 4 SPI Compatible Control Interface Input Timing
LSB
LSB
Test Conditions
AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, TA = +25oC, fs = 48kHz, MCLK and ADCMCLK = 256fs unless
otherwise stated
PARAMETER
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
SCLK duty cycle
SDIN to SCLK set-up time
SDIN hold time from SCLK rising edge
SDO propagation delay from SCLK rising
edge
CSB pulse width high
CSB rising/falling to SCLK rising
SCLK glitch suppression
SYMBOL
tSCS
tSCY
tDSU
tDHO
tDL
tCSH
tCSS
tps
MIN
60
80
40/60
20
20
20
20
2
Table 6 3-wire SPI Compatible Control Interface Input Timing Information
TYP
MAX
UNIT
ns
ns
60/40
ns
ns
ns
5
ns
ns
ns
8
ns
CONTROL INTERFACE TIMING – 2-WIRE MODE
t
3
SDIN
t
t
5
3
t
t
t
t
6
2
4
8
SCLK
t
1
t
t
9
7
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
w
PD Rev 4.0 April 2007
18
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