S6B0796 View Datasheet(PDF) - Samsung
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S6B0796 Datasheet PDF : 32 Pages
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240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0
S6B0796
DISPOFFB
FR
MD
DI7
S/C
DI0 – DI6
XCK
Y1 – Y240
Control input pin for output deselect level
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
. When set to VSS level “L”, the LC drive output pins(Y1-Y240) are set to level
V5.
. While set to “L”, the contents of the shift resister are reset not reading data.
When the DISPOFFB function is canceled, the driver outputs deselect
Level(V12 or V43), and the shift data is reading on the falling edge of the LP.
That time, if DISPOFFB removal time can not keep regulation what is
shown AC characteristics (page 26), the shift data is not reading correctly.
AC signal input for LC driving waveform
. The input signal is level-shifted from logic voltage level to LC drive voltage
level, and controls LC drive circuit.
. Normally, input a frame inversion signal.
. The LC driver output pin’s output voltage level can be set using the shift
register output signal and the FR signal.
Table of truth values is shown in table 4.
Mode selection pin
. When set to VSS level “L”, Single mode operation is selected, when set to
VDD level “H”, Dual mode operation is selected.
Dual Mode data input pin
. According to the data shift direction of the data shift register, data can be
input starting from the 121st bit.
When the chip is used as Dual mode, DI7 will be pull-down.
When the chip is used as Single mode, DI7 won’t be pull-down.
Segment mode/common mode selection pin
. When set to VSS level ‘L”, common mode is set.
Not used
. Connect DI0 – DI6 to VSS or VDD. Avoiding floating.
Not used
. XCK is pull-down in common mode, so connect to VSS or open.
LC driver output pins
. Corresponding directly to each bit of the shift register, one level(V0, V12,
V43, or V5) is selected and output. Table of truth values is shown in table 4.
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