S6B0796 View Datasheet(PDF) - Samsung

Part Name

Description

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S6B0796

240 SEG / COM DRIVER FOR STN LCD

Samsung 

240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0

S6B0796

FR

MD

S/C

EIO1

EIO2

Y1 – Y240

AC signal input for LC driving waveform

. The input signal is level-shifted from logic voltage level to LC drive voltage

level, and controls LC drive circuit.

. Normally, inputs a frame inversion signal.

. The LC driver output pin’s output voltage level can be set using the line

latch output signal and the FR signal.

Table of truth values is shown in table 4.

Mode selection pin

. When set to VSS level “L”, 8-bit parallel input mode is set.

. When set to VDD level “H”, 4-bit parallel input mode is set.

. The relationship between the display data and driver output pins is shown

in table 5.

Segment mode/common mode selection pin

. When set to VDD level ‘H”, segment mode is set.

Input / output pin for chip selection

. When L/R input is at VSS level ‘L”, EIO1 is set for output, and EIO2 is set for

input.

. When L/R input is at VDD level ‘H”, EIO1 is set for input, and EIO2 is set for

output.

. During output. set to “H” while LP*XCLKB is ‘H” and after 240-bits of data

have been read, set to “L” for one cycle (from falling edge to falling edge of

XCK), after which it returns to “H”.

. During input, after the LP signal is input, the chip is selected while EI is set

to “L”. After 240-bits of data have been read, the chip is deselected.

LC driver output pins

. Corresponding directly to each bit of the data latch, one level(V0, V12, V43,

or V5) is selected and output.

Table of truth values is shown in table 4.

12

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