PT6301
2nd Byte
(7th)
6th Byte
(11th)
MSB
LSB
B7 B6 B5 B4 B3 B2 B1
* C30 C25 C20 C15 C10 C5
B0 Specifies 1st column data
C0 (written into CGRAM address 01H)
:
:
MSB
LSB
B7 B6 B5 B4 B3 B2 B1
* C34 C29 C24 C19 C14 C9
B0 Specifies 5th column data
C4 (written into CGRAM address 01H)
X0 (LSB) to X3 (MSB): CGRAM address (4 bits 16 characters)
C0 (LSB) to C34 (MSB): Character pattern data (35 bits: 35 outputs per character)
*: Don’t care.
CGRAM ADDRESSES AND CORRESPONDING CGROM ADDRESS
HEX X3 X2 X1 X0
CGROM address
0
0
0
0
0
RAM00 (00000000B)
1
0
0
0
1
RAM01 (00000001B)
2
0
0
1
0
RAM02 (00000010B)
3
0
0
1
1
RAM03 (00000011B)
4
0
1
0
0
RAM04 (00000100B)
5
0
1
0
1
RAM05 (00000101B)
6
0
1
1
0
RAM06 (00000110B)
7
0
1
1
1
RAM07 (00000111B)
8
1
0
0
0
RAM08 (00001000B)
9
1
0
0
1
RAM09 (00001001B)
A
1
0
1
0
RAM0A (00001010B)
B
1
0
1
1
RAM0B (00001011B)
C
1
1
0
0
RAM0C (00001100B)
D
1
1
0
1
RAM0D (00001101B)
E
1
1
1
0
RAM0E (00001110B)
F
1
1
1
1
RAM0F (00001111B)
Note: Refer to ROM code tables
V1.2
11
March 2012