UPD45128163-I-E View Datasheet(PDF) - Elpida Memory, Inc

Part Name

Description

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UPD45128163-I-E

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Elpida Memory, Inc 

µPD45128163-I-E

11.3 Write to Read Command Interval

Write command and Read command interval is also 1 cycle.

Only the write data before Read command will be written.

The data bus must be Hi-Z at least one cycle prior to the first DOUT.

Burst length = 4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

/CAS latency = 2

Command

DQ

WRITE A READ B

Hi-Z

DA1

QB1

QB2

QB3

QB4

/CAS latency = 3

Command

DQ

WRITE A READ B

Hi-Z

DA1

QB1

QB2

QB3

QB4

Data Sheet E0729N10 (Ver. 1.0)

27

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