NOIL1SM4000A(2013) View Datasheet(PDF) - ON Semiconductor

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NOIL1SM4000A
(Rev.:2013)

LUPA4000: 4 MegaPixel High Speed CMOS Sensor

ON Semiconductor 

NOIL1SM4000A

Pixel Array Drivers

The image sensor has on-chip drivers for the pixel array

signals The driving on system level is easy and flexible; the

maximum currents applied to the sensor are also controlled

on-chip. This means that the charging on sensor level is

fixed; the sensor cannot be overdriven externally. The

operation of the on-chip drivers is explained in Timing and

Readout of Image Sensor on page 13.

Column Amplifiers

The column amplifiers are designed for minimum power

dissipation and minimum loss of signal, resulting in multiple

biasing signals.

The column amplifiers have an integrated

‘voltage-averaging’ feature. In the voltage-averaging mode,

the voltage average between two columns is read out. In this

mode, only 2:1 pixels must be read out.

To achieve the voltage-averaging mode, an additional

external digital signal called voltage-averaging is required

in combination with a bit from the SPI.

Analog-to-Digital Converter

The LUPA4000 has two 10-bit flash ADCs running

nominally at 10 Msamples/s. The ADC block is electrically

separated from the image sensor. The inputs of the ADC

must be tied externally to the outputs of the output

amplifiers. If the internal ADC is not used, then the power

supply pins to the ADC and the I/Os must be grounded.

Even in this configuration, the internal ADCs are not able

to sustain the 66 Mpixel/sec provided by the output

amplifier when run at full speed.

One ADC samples the even columns and the second ADC

samples the odd columns. Although the input range of the

ADC is between 1 V and 2 V and the output range of the

analog signal is between 0.3 V and 1.3 V, the analog output

and digital input may be tied to each other directly. This is

possible because there is an on-chip level-shifter located in

front of the ADC to lift up the analog signal to the ADC

range.

Errata for Internal ADCs

Use external ADCs due to the limitation of the internal

ADC clock, not operational at system clock. No fix is

intended to resolve this limitation.

Table 1. ADC SPECIFICATIONS

Parameter

Specification

Input range

1 V to 2 V (Note 1)

Quantization

10 bits

Normal data rate

10 Msamples/s

Differential nonlinearity (DNL) - Typ. < 0.4 LSB RMS

linear conversion mode

Integral nonlinearity (INL) -

linear conversion mode

Typ. < 3.5 LSB

Input capacitance

< 2 pF

Power dissipation at 33 MHz 50 mW

Conversion law

Linear/Gamma−corrected

1. The internal ADC range is typically 50 mW lower than the external

applied ADC_VHIGH and ADC_VLOW voltages due to voltage

drops over parasitic internal resistors in the ADC.

ADC Timing

The ADC converts the pixel data on the falling edge of the

ADC_CLOCK, but it takes two clock cycles before this

pixel data is at the output of the ADC. This pipeline delay is

shown in Figure 6.

Figure 6. ADC Timing

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