NOIL1SM4000A(2013) View Datasheet(PDF) - ON Semiconductor
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NOIL1SM4000A Datasheet PDF : 30 Pages
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NOIL1SM4000A
SENSOR ARCHITECTURE
The LUPA4000 architecture is shown in Figure 4.
Image Core
The image core consists of a pixel array, one X-addressing
and two Y-addressing registers (only one drawn), pixel array
drivers, and column amplifiers.
The active pixel area is read out in progressive scan by one
or two output amplifiers. The output amplifiers operate at a
nomimal speed of 66-MHz pixel rate, or 33-MHz pixel rate
if two output amplifiers are used to read out the imager. The
image sensor is designed for operation up to 66 MHz.
The structure allows having a programmable addressing
in the x-direction and y-direction in steps of two. Only even
start addresses in x-direction and y-direction are possible.
The starting point of the address can be uploaded using the
SPI.
Eos_y
On-chip drivers
(reset, mem_hl, precharge, sample)
Pixel Array
(2048 x 2048)
Clk_y Sync_y
Pixel
(0,0)
Column Amplifiers
X-shift registers
Logic
Blocks
SPI
DAC
Eos_x
Clk_x Sync_x
2 Differential Outputs
Figure 4. Block Diagram of Image Sensor
Output Amplifier
The sensor has two output amplifiers. A single amplifier
can be operated at 66 Mpixels/sec to bring the whole pixel
array of 2048 by 2048 pixels at the required frame rate. The
second output amplifier can be enabled in parallel if the
clock frequency is decreased to 33 Msamples/sec. Using
only one output-stage, the output signal is the result of
multiplexing between the two internal buses. When using
two output-stages, both outputs are in phase.
Each output-stage has two outputs. One output is the pixel
signal; the second output is a DC signal, which offset can be
programmed using a 7-bit word. The DC signal is used for
common mode rejection between the two signals. The
disadvantage is an increase in power dissipation. However,
this can be reduced by setting the highest DAC voltage using
the SPI.
Image Sensor
7 bits
SPI
DAC
Output 1
(Pixel Signal)
Output 2
(dc signal)
Figure 5. Output Stage Architecture
The output voltage of Output 1 is between 1.3 V (dark
level) and 0.3 V (white level) and depends on process
variations and voltage supply settings. The output voltage of
Output2 is determined by the DAC.
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