MM912G634CM1AE View Datasheet(PDF) - Freescale Semiconductor
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MM912G634CM1AE Datasheet PDF : 345 Pages
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Pin Assignment
2.1 MM912_634 Pin Description
The following table gives a brief description of all available pins on the MM912_634 package. Refer to the highlighted chapter for
detailed information.
Table 4. MM912_634 Pin Description
Pin #
Pin Name
Formal Name
Description
1
PA6
2
PE0/EXTAL
3
PE1/XTAL
4
TEST
5
PA5
6
PA4
7
PA3
8
PA2
9
PA1
MCU PA6
MCU Oscillator
MCU Oscillator
MCU Test
MCU PA5
MCU PA4
MCU PA3 / SS
MCU PA2 / SCK
MCU PA1 / MOSI
General purpose port A input or output pin 6. See Section 4.28, “Port Integration
Module (S12IPIMV1)
EXTAL is one of the optional crystal/resonator driver and external clock pins. On
reset, all the device clocks are derived from the Internal Reference Clock and port
PE may be used for general purpose I/O. See Section 4.38.2.2, “EXTAL and XTAL
and Section 4.28, “Port Integration Module (S12IPIMV1).
XTAL is one of the optional crystal/resonator driver and external clock pins. On
reset, all the device clocks are derived from the Internal Reference Clock and port
PE may be used for general purpose I/O. See Section 4.38.2.2, “EXTAL and XTAL
and Section 4.28, “Port Integration Module (S12IPIMV1).
This input only pin is reserved for test. This pin has a pull-down device. The TEST
pin must be tied to EVSS in user mode.
General purpose port A input or output pin 5. See Section 4.28, “Port Integration
Module (S12IPIMV1)
General purpose port A input or output pin 4. See Section 4.28, “Port Integration
Module (S12IPIMV1).
General purpose port A input or output pin 3, shared with the SS signal of the
integrated SPI Interface. See Section 4.28, “Port Integration Module (S12IPIMV1).
General purpose port A input or output pin 2, shared with the SCLK signal of the
integrated SPI Interface. See Section 4.28, “Port Integration Module (S12IPIMV1).
General purpose port A input or output pin 1, shared with the MOSI signal of the
integrated SPI Interface. See Section 4.28, “Port Integration Module (S12IPIMV1).
10
PA0
MCU PA0 / MISO
General-purpose port A input or output pin 0, shared with the MISO signal of the
integrated SPI Interface. See Section 4.28, “Port Integration Module (S12IPIMV1).
11
VSSRX
MCU 5.0 V Ground Ground for the MCU 5.0 V power supply.
12
VDDRX
MCU 5.0 V Supply
MCU 5.0 V - Core- and Flash Voltage Regulator supply. See Section 4.27,
“MM912_634 - MCU Die Overview.
13
VSSD2D
MCU 2.5 V Ground Ground for the MCU 2.5 V power supply.
14
VDDD2D
MCU 2.5 V Supply
MCU 2.5 V - MCU Die-to-Die Interface power supply. See Section 4.27,
“MM912_634 - MCU Die Overview.
15
VDD
Voltage Regulator
Output 2.5 V
+2.5 V main voltage regulator output pin. External capacitor (CVDD) needed. See
Section 4.5, “Power Supply.
16
VDDX
Voltage Regulator Output +5.0 V main voltage regulator output pin. External capacitor (CVDDX) needed. See
5.0 V
Section 4.5, “Power Supply.
17
DGND
Digital Ground
This pin is the device digital ground connection for the 5.0 V and 2.5V logic. DGND,
LGND, and AGND are internally connected to PGND via a back to back diode.
18
VSENSE
Voltage Sense
Battery voltage sense input. This pin can be connected directly to the battery line for
voltage measurements. The voltage present at this input is scaled down by an
internal voltage divider, and can be routed to the internal ADC via the analog
multiplexer.The pin is self-protected against reverse battery connections. An
external resistor (RVSENXSE) is needed for protection(6). See Section 4.23,
“Supply Voltage Sense - VSENSE. Note: This pin function is not available on all
device configurations.
Note:
6. An optional filter capacitor CVSENSE is recommended to be placed between the board connector and DVSENSE to GND for increased
ESD performance.
MM912_634 Advance Information, Rev. 4.0
Freescale Semiconductor
8
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