M2V64S20BTP View Datasheet(PDF) - Mitsumi

Part Name

Description

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M2V64S20BTP

64M bit Synchronous DRAM

Mitsumi 

PC133 SDRAM (Rev.0.5)

Oct. '99

64M bit Synchronous DRAM

MITSUBISHI LSIs

M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)

M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)

M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)

[ BURST WRITE ]

A burst write operation is enabled by setting A9=0 at MRS. A burst write starts in

the same cycle as a write command set. (The latency of data input is 0.) The

burst length can be set to 1,2,4,8, and full-page, like burst read operations.

tRCD

CLK

Command

ACT

WRITE

Address

DQ

DQ

DQ

DQ

DQ

D0

D0 D1

D0 D1 D2 D3

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

Dm D0 D1

BL=1

BL=2

BL=4

BL=8

BL=FP

M2V64S20B : m=1023

M2V64S30B : m=511

M2V64S40B : m=255

Full Page counter rolls over

and continues to count.

[ SINGLE WRITE ]

A single write operation is enabled by setting A9=1 at MRS. In a single write

operation, data is written only to the column address specified by the write

command set cycle without regard to the burst length setting. (The latency of data

input is 0.)

CLK

Command

Address

DQ

ACT

X

tRCD

WRITE

Y

D0

MITSUBISHI ELECTRIC

19

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