M2V64S20BTP View Datasheet(PDF) - Mitsumi

Part Name

Description

View to exact match

M2V64S20BTP

64M bit Synchronous DRAM

Mitsumi 

PC133 SDRAM (Rev.0.5)

Oct. '99

64M bit Synchronous DRAM

MITSUBISHI LSIs

M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT)

M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT)

M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)

CLK

Command

A0-9

A10

A11

BA0,1

DQ

CLK

Command

A0-9

A10

A11

BA0,1

DQ

CLK

Command

CL=3 DQ

CL=2 DQ

Multi Bank Interleaving READ (BL=4, CL=3)

ACT

Xa

tRCD

READ ACT

Y

Xb

READ PRE

Y

Xa

0

Xb

00

Xa

Xb

00

00 10

10 00

Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2

/CAS latency

Burst Length

READ with Auto-Precharge (BL=4, CL=3)

ACT

Xa

tRCD

READ

Y

BL + tRP

ACT

BL

tRP

Xa

Xa

1

Xa

Xa

Xa

00

00

00

Qa0 Qa1 Qa2 Qa3

Internal precharge start

READ Auto-Precharge Timing (BL=4)

ACT

READ

BL

Qa0 Qa1 Qa2 Qa3

Qa0 Qa1 Qa2 Qa3

Internal Precharge Start Timing

MITSUBISHI ELECTRIC

17

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