ISL8560 View Datasheet(PDF) - Intersil

Part Name

Description

View to exact match

ISL8560

DC/DC Power Switching Regulator

Intersil 

ISL8560

Compensation Break Frequency

Equations

fZ1

=

----------------------------1-----------------------------

2

π

⋅

-(--R----4-----⋅---g---m------+-----1----)

gm

⋅

C6

fP1

=

------------1--------------

2πR6 ⋅ C7

fZ2

=

------------1--------------

2πR2 ⋅ C7

fP2

=

--------------1---------------

2πR4 ⋅ C10

(EQ. 12)

Assumption: R6<<R2, R6<<R3, and C10<<C6.

Figure 31 shows an asymptotic plot of the DC/DC

converter’s gain vs frequency. The actual Modulator Gain

has a high gain peak due to the high Q factor of the output

filter and is not shown in Figure 31. Using the guidelines on

page 14 should give a Compensation Gain similar to the

curve plotted. The open loop error amplifier gain bounds the

compensation gain. Check the compensation gain at FP2

with the capabilities of the error amplifier. The Closed Loop

Gain is constructed on the graph of Figure 31 by adding the

Modulator Gain (in dB) to the Compensation Gain (in dB).

This is equivalent to multiplying the modulator transfer

function to the compensation transfer function and plotting

the gain.

The compensation gain uses external impedance networks

ZFB and ZIN to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin.

100

FZ1 FZ2 FP1 FP2

80

OPEN LOOP

60

ERROR AMP GAIN

40

20LOG

20 (R4/R2)

20LOG

(VIN/ΔVOSC)

0

MODULATOR

-20

GAIN

-40

FLC

FESR

-60

10

100

1k

10k 100k

COMPENSATION

GAIN

CLOSED LOOP

GAIN

1M 10M

FREQUENCY (Hz)

FIGURE 31. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

A more detailed explanation of voltage mode control of a

buck regulator can be found in Tech Brief TB417, titled

“Designing Stable Compensation Networks for Single Phase

Voltage Mode Buck Regulators.”

Layout Considerations

Layout is very important in high frequency switching

converter design. With power devices switching efficiently

between 100kHz and 600kHz, the resulting current

transitions from one device to another cause voltage spikes

across the interconnecting impedances and parasitic circuit

elements. These voltage spikes can degrade efficiency,

radiate noise into the circuit, and lead to device overvoltage

stress. Careful component layout and printed circuit board

design minimizes these voltage spikes.

As an example, consider the turn-off transition of the control

MOSFET. Prior to turn-off, the MOSFET is carrying the full

load current. During turn-off, current stops flowing in the

MOSFET and is picked up by the freewheeling Schottky

diode. Any parasitic inductance in the switched current path

generates a large voltage spike during the switching interval.

Careful component selection, tight layout of the critical

components, and short, wide traces minimizes the

magnitude of voltage spikes.

There are two sets of critical components in the ISL8560

switching converter. The switching components are the most

critical because they switch large amounts of energy, and

therefore tend to generate large amounts of noise. Next are

the small signal components which connect to sensitive

nodes or supply critical bypass current and signal coupling.

VIN

ISL8560

CBP2 VCC5

LX

COMP

PGND

FB

VIN

CIN

L

VOUT1

D

COUT1

C6

R4

C10

R2

R3

C7 R6

GND PAD

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 32. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

15

FN9244.7

September 19, 2008

Share Link: