ISL8560 View Datasheet(PDF) - Intersil
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ISL8560 Datasheet PDF : 17 Pages
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ISL8560
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25 times greater than the maximum input voltage,
while a voltage rating of 1.5 times is a conservative
guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current through the input capacitors
may be closely approximated through Equation 10:
V-----O----U---T-
VIN
×
⎛
⎜
⎝
IO
UTM
A
2
X
×
⎛
⎝
1
–
V---V--O--I--UN---T-⎠⎞
+
--1----
12
×
⎛
⎜
⎝
V-----I-N-----–-----V----O----U---T-
L × fOSC
×
-V--V--O--I--UN---T-⎠⎟⎞
2⎞
⎟
⎠
(EQ. 10)
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
Feedback Compensation
Figure 30 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The error
amplifier output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the LX node. The PWM
wave is smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at fLC and a zero at fESR. The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage ΔVOSC. The ISL8560
incorporates a feed forward loop that accounts for changes
in the input voltage. This maintains a constant modulator
gain.
Modulator Break Frequency Equations
fLC=
---------------------1---------------------
2π x LO x CO
fESR=
---------------------1----------------------
2π x ESR x CO
(EQ. 11)
The compensation network consists of the transconductance
amplifier (internal to the ISL8560) and the impedance
networks ZIN and ZFB. The goal of the compensation
network is to provide a closed loop transfer function with the
highest 0dB crossing frequency (f0dB) and adequate phase
margin. Phase margin is the difference between the closed
loop phase at f0dB and 180°. The equations in the following
section relate the compensation network’s poles, zeros and
gain to the components (R2, R3, R4, R6, C10, C6, and C7) in
OSC
PWM
COMPARATOR
-
Δ VOSC
+
DRIVER
DRIVER
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
VIN
LO
LX
CO
D
ESR
(PARASITIC)
VOUT
DETAILED COMPENSATION COMPONENTS
C10
C6
R4
ZFB
VOUT
ZIN
C7 R6
R2
COMP
FB
gm-
+
R3
ISL8560
REFERENCE
VOUT
=
1.2
0
×
⎛
⎜
⎝
1
+
R-R----23- ⎠⎟⎞
FIGURE 30. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
Figure 30. Use these guidelines for locating the poles and
zeros of the compensation network:
1. Pick Gain (R3gm/(R2+R3) for desired converter
bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% fLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at Half the Switching Frequency.
6. Check Gain against Error transconductance’s Open-
Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
14
FN9244.7
September 19, 2008
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