EDS2516APTA-75TI-E View Datasheet(PDF) - Elpida Memory, Inc
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EDS2516APTA-75TI-E Datasheet PDF : 52 Pages
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EDS2516APTA-TI-E
DC Characteristics 2 (TA = –40 to +85°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
Symbol min.
max.
Unit
Test condition
Input leakage current
ILI
–1
1
Output leakage current
ILO
–1.5
1.5
Output high voltage
VOH
2.4
—
Output low voltage
VOL
—
0.4
µA
0 ≤ VIN ≤ VDD
µA
0 ≤ VOUT ≤ VDD, DQ = disable
V
IOH = –4 mA
V
IOL = 4 mA
Notes
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V ± 0.3V)
Parameter
Symbol Pins
min.
typ.
max.
Unit
Input capacitance
CI1
CLK
2.5
—
CI2
Address, CKE, /CS, /RAS, /CAS,
/WE, UDQM and LDQM,
2.5
—
Data input/output capacitance CI/O DQ
4
—
3.5
pF
3.8
pF
6.5
pF
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.
3. UDQM and LDQM = VIH to disable DOUT.
4. This parameter is sampled and not 100% tested.
Notes
1, 2, 4
1, 2, 4
1, 2, 3, 4
AC Characteristics (TA = –40 to +85°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
-75
Parameter
Symbol
min.
max.
Unit
System clock cycle time
tCK
7.5
—
ns
CLK high pulse width
tCH
2.5
—
ns
CLK low pulse width
tCL
2.5
—
ns
Access time from CLK
tAC
—
5.4
ns
Data-out hold time
tOH
2.7
—
ns
CLK to Data-out low impedance
tLZ
1
—
ns
CLK to Data-out high impedance
tHZ
—
5.4
ns
Input setup time
tSI
1.5
—
ns
Input hold time
tHI
0.8
—
ns
Ref/Active to Ref/Active command period
tRC
67.5
—
ns
Active to Precharge command period
Active command to column command
(same bank)
Precharge to active command period
tRAS
45
tRCD
20
tRP
20
120000
ns
—
ns
—
ns
Write recovery or data-in to precharge lead time tDPL
15
—
ns
Last data into active latency
tDAL
2CLK + 20ns —
Active (a) to Active (b) command period
tRRD
15
—
ns
Transition time (rise and fall)
tT
0.5
5
ns
Refresh period
(8192 refresh cycles)
tREF
—
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
2. Access time is measured at 1.4V. Load condition is CL = 50pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Notes
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1
1
1
1
1
1
1
1
Data Sheet E0677E10 (Ver. 1.0)
6
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