EDS2516APTA-75TI-E View Datasheet(PDF) - Elpida Memory, Inc
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EDS2516APTA-75TI-E Datasheet PDF : 52 Pages
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EDS2516APTA-TI-E
DC Characteristics 1 (TA = –40 to +85°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol Grade
max.
Unit
Test condition
Notes
Operating current
ICC1
115
mA
Burst length = 1
tRC = tRC (min.)
1, 2, 3
Standby current in power down
ICC2P
3
mA
CKE = VIL, tCK = tCK (min.) 6
Standby current in power down
(input signal stable)
Standby current in non power down
Standby current in non power down
(input signal stable)
ICC2PS
ICC2N
ICC2NS
2
mA
CKE = VIL, tCK = ∞
7
20
mA
CKE, /CS = VIH,
tCK = tCK (min.).
4
9
mA
CKE = VIH, tCK = ∞,
/CS = VIH
8
Active standby current in power down ICC3P
4
mA
CKE = VIL, tCK = tCK (min.) 1, 2, 6
Active standby current in power down
(input signal stable)
Active standby current in non power
down
Active standby current in non power
down (input signal stable)
ICC3PS
ICC3N
ICC3NS
3
mA
CKE = VIL, tCK = ∞
2, 7
30
mA
CKE, /CS = VIH,
tCK (min.)
1, 2, 4
15
mA
CKE = VIH, tCK = ∞,
/CS = VIH
2, 8
Burst operating current
ICC4
145
mA
tCK = tCK (min.), BL = 4
1, 2, 5
Refresh current
ICC5
220
mA
tRC = tRC (min.)
3
Self refresh current
ICC6
3
mA
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Data Sheet E0677E10 (Ver. 1.0)
5
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