EDS1232AATA-60TI View Datasheet(PDF) - Elpida Memory, Inc
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Description
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EDS1232AATA-60TI Datasheet PDF : 53 Pages
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EDS1232AATA-TI
Relationship Between Frequency and Minimum Latency
Parameter
-60
-75
Frequency (MHz)
166
133
133
100
tCK (ns)
Symbol 6
7.5
7.5
10
Unit
Active command to column command
(same bank)
lRCD
3
2
3
2
tCK
Active command to active command
(same bank)
lRC
10
8
9
7
tCK
Active command to precharge command
(same bank)
lRAS
7
6
6
5
tCK
Precharge command to active command
(same bank)
lRP
3
2
3
2
tCK
Write recovery or data-in to precharge
command (same bank)
lDPL
2
2
2
2
tCK
Active command to active command
(different bank)
lRRD
2
2
2
2
tCK
Self refresh exit time
lSREX 1
1
1
1
tCK
Last data in to active command
(Auto precharge, same bank)
lDAL
5
4
5
4
tCK
Self refresh exit to command input
lSEC
10
8
9
7
tCK
Precharge command to high impedance
(CL = 2)
lHZP
2
2
tCK
(CL = 3)
Last data out to active command
(auto precharge) (same bank)
Last data out to precharge
(early precharge)
(CL = 2)
(CL = 3)
lHZP
3
3
3
3
tCK
lAPR
1
1
1
1
tCK
lEP
–1
–1
tCK
lEP
–2
–2
–2
–2
tCK
Column command to column command lCCD
1
1
1
1
tCK
Write command to data in latency
lWCD
0
0
0
0
tCK
DQM to data in
lDID
0
0
0
0
tCK
DQM to data out
CKE to CLK disable
lDOD
2
2
2
2
tCK
lCLE
1
1
1
1
tCK
Register set to active command
/CS to command disable
lMRD
2
2
lCDD
0
0
2
2
tCK
0
0
tCK
Power down exit to command input
lPEC
1
1
1
1
tCK
Notes: 1. lRCD to lRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
Notes
1
1
1
1
1
1
2
= [lDPL + lRP]
= [lRC]
3
Data Sheet E0305E30 (Ver. 3.0)
8
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