CY7C4215-15AXI(2011) View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

View to exact match

CY7C4215-15AXI
(Rev.:2011)

256/512/1K/4K x 18 Synchronous FIFOs

Cypress Semiconductor 

CY7C4205/CY7C4215

CY7C4225/CY7C4245

Switching Waveforms (continued)

Figure 12. Programmable Almost Empty Flag Timing

tCLKH

tCLKL

WCLK

WEN

tENS tENH

PAE [24]

RCLK

REN

tPAE

n+1WORDS

IN FIFO

tPAE

tENS

n WORDS IN FIFO

Figure 13. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)

WCLK

tCLKH

WEN

PAE

RCLK

REN

tCLKL

tENS tENH

tSKEW3 [26]

Note 25

tPAEsynch

N + 1 WORDS

INFIFO

tENS

tENS tENH

Note 27 tPAEsynch

Notes:

24. PAE offset n. Number of data words into FIFO already = n.

25. PAE offset n.

26.

atSnKdEWth3eisristhinegmRiCniLmKuims

time between a rising WCLK and a rising RCLK edge for PAE to change

less than tSKEW3, then PAE may not change state until the next RCLK.

state

during

that

clock

cycle.

If

the

time

between

the

edge

of

WCLK

27. If a read is performed on this rising edge of the read clock, there will be Empty + (n1) words in the FIFO when PAE goes LOW.

Document Number: 001-45652 Rev. *B

Page 16 of 25

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