CY7C4215-15AXI(2011) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
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CY7C4215-15AXI Datasheet PDF : 25 Pages
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CY7C4205/CY7C4215
CY7C4225/CY7C4245
Switching Waveforms (continued)
WCLK
D0–D17
FF
NO WRITE
tSKEW1[17]
tWFF
Figure 10. Full Flag Timing
NO WRITE
tDS
tSKEW1[17]
DATA WRITE
tWFF
tWFF
DATA WRITE
WEN
RCLK
REN
tENS
tENH
tENS
tENH
OE
Q0–q17
LOW
tA
DATA IN OUTPUT REGISTER
DATAREAD
tA
NEXT DATA READ
WCLK
WEN
HF
RCLK
REN
Figure 11. Half-Full Flag Timing
tCLKH
tCLKL
tENS tENH
tHF
HALF FULL OR LESS
HALF FULL+1
OR MORE
tHF
tENS
HALF FULL OR LESS
Note
23.
tthSKeErWis1inigs
the minimum time between a
edge of RCLK and the rising
rising
edge
RCLK edge
of WCLK is
and
less
a rising WCLK edge to guarantee that FF will go HIGH during the
than tSKEW1, then FF may not change state until the next WCLK
current
edge.
clock
cycle.
If
the
time
between
Document Number: 001-45652 Rev. *B
Page 15 of 25
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