ADN2816 View Datasheet(PDF) - Analog Devices

Part Name

Description

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ADN2816

Continuous Rate 10 Mb/s to 675 Mb/s Clock and Data Recovery IC

Analog Devices 

ADN2816

Additional Features Available via the I2C Interface

Coarse Data Rate Readback

The data rate can be read back over the I2C interface to

approximately ±10% without the need of an external reference

clock. A 9-bit register, COARSE_RD[8:0], can be read back

when LOL is deasserted. The eight MSBs of this register are the

contents of the RATE[7:0] register. The LSB of the

COARSE_RD register is Bit MISC[0].

Table 13 provides coarse data rate readback to within ±10%.

Data Sheet

System Reset

A frequency acquisition can be initiated by writing a 1 followed

by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new

frequency acquisition while keeping the ADN2816 in the

operating mode that it was previously programmed to in

Registers CTRL[A], CTRL[B], and CTRL[C].

Rev. C | Page 18 of 24

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