A1374 View Datasheet(PDF) - Allegro MicroSystems
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A1374 Datasheet PDF : 22 Pages
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A1373 and
A1374
High Precision, Output Pin Programmable
Linear Hall Effect Sensors
The mid voltage range, VPM , is a neutral level used to separate
VPH and VPL pulses from each other.
The low level, VPL, pulse is used to increment the mode, register,
and bitfield addresses that are to be set. The device generates a
VPL pulse on the falling edge of the mid-level to low-level transi-
tion, VPM to VPL.
In Try Value mode,the programming drive signal can be held
at 5 V or less if no code search is required. If a code search is
required, then the output drive signal must be released to allow
the output level to be read for each bitfield increment (see panels
A and B, below).
To guarantee proper pulse recognition, each level must be held
for the predefined durations specified in the Programming Proto-
col Characteristics table. Failure to follow the specifications may
produce undefined results. Examples of common pulse trains are
shown in panels C and D, below.
Mode Select Register Select
(Code 1)
(Code 3)
30
25
20
tPME
tPLA tPMA
15
tPHE
Bitfield Select
(Code 10)
= Programming edge
Mode Select
(Code 1)
} VPH
Mode Select Register Select
(Code 1)
(Code 3)
30
25
20
Bitfield Select
(Code 10)
Mode Select
(Code 1)
} VPH
Removing the output drive signal after each
VPM allows measurement of the output pin
} VPM
15
} VPM
10
1
123
1 2 3 4 5 6 7 8 9 10
1
10
1
123
1 2 3 4 5 6 7 8 9 10
1
5
Try Mode
selected
0
Sensitivity Fine selected
(Sensitivity Coarse)
(Qvo Fine)
10th address
selected
Try Mode
selected
5
VPL
2.0
0
VOUT measurements 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
2.0
VPL
Time (μs)
A. Try Value Mode. Code search with drive signal held
at 5 V.
Time (μs)
B. Try Value Mode. Code search with drive signal released
after each VPM, allows output to be measured after each code
increment.
Mode Select
(Code 2)
Register Select
(Code 3)
30
25
Blow
Sensitivity
Fuse
Fine
mode
register
selected
selected
20
15
Bitfield Select
(Code 8)
Bitfield 8
address
selected
Blow Fuse
} VPH
30
25
20
} VPM
15
10
12
12 3
1 2 3 45 6 7 8
5
0
10
5
VPL
0
Mode Select
(Code 3)
Register Select Bitfield Select Lock (blow Lock Bit fuse)
(Code 0)
(Code 1)
tPME
Lock
Device
mode
selected
tPLA tPMA
tPHE
1
2
3
tPHP
1
1
Holding at VPM is allowed when no
VPL is required; dropping to VPL
will increment by 1 bitfield
} VPH
} VPM
VPL
Time (μs)
C. Blow Fuse Mode: Code 8 / bit 4 is programmed.
Time (us)
D. Lock Device Mode. Device-level Lock Bit is programmed;
device programming is then permanently disabled.
Allegro MicroSystems, Inc.
16
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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