MT48LC4M8A1TG-10 View Datasheet(PDF) - Micron Technology
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MT48LC4M8A1TG-10 Datasheet PDF : 50 Pages
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16 MEG: x4, x8
SDRAM
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Figure 11 for each possible CAS latency; data
element n + 3 is either the last of a burst of four or the last
desired of a longer burst. Follow-ing the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until tRP is met. Note that part of the
row precharge time is hidden during the access of the last
data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the op-
timum time (as described above) provides the same op-
Figure 11
READ to PRECHARGE
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
t RP
NOP
PRECHARGE
NOP
NOP
X = 0 cycles
BANK
(a or all)
T7
ACTIVE
BANK a,
ROW
DQ
DOUT
n
CAS Latency = 1
DOUT
n+1
DOUT
n+2
DOUT
n+3
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
t RP
NOP
PRECHARGE
NOP
NOP
X = 1 cycle
BANK
(a or all)
T7
ACTIVE
BANK a,
ROW
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 2
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
T0
T1
CLK
COMMAND
READ
NOP
ADDRESS
BANK a,
COL n
T2
NOP
T3
T4
T5
T6
T7
t RP
NOP
PRECHARGE
NOP
NOP
X = 2 cycles
BANK
(a or all)
ACTIVE
BANK a,
ROW
DQ
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 3
NOTE: DQM is LOW.
DON’T CARE
18
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©1998, Micron Technology, Inc.
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