MT48LC4M8A1TG-10 View Datasheet(PDF) - Micron Technology
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MT48LC4M8A1TG-10 Datasheet PDF : 50 Pages
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16 MEG: x4, x8
SDRAM
following a previous WRITE command. Full-speed ran-
dom write accesses can be performed to the same bank,
as shown in Figure 16, or each subsequent WRITE may be
performed to a different bank.
A fixed-length WRITE burst may be followed by, or
truncated with, a READ burst (provided that auto
precharge was not activated), and a full-page WRITE
burst can be truncated with a subsequent READ burst.
Once the READ command is registered, the data inputs
will be ignored, and WRITEs will not be executed. An
example is shown in Figure 17. Data n + 1 is either the last
of a burst of two or the last desired of a longer burst.
A fixed-length WRITE burst may be followed by, or
truncated with, a PRECHARGE command to the same
Figure 16
RANDOM WRITE Cycles
T0
T1
T2
T3
CLK
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DQ
DIN
n
DIN
DIN
a
x
DIN
m
NOTE: Each WRITE command may be to either bank. DQM is
LOW.
Figure 17
WRITE to READ
T0
T1
T2
T3
T4
T5
CLK
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
BANK,
COL b
DQ
DIN
n
DIN
n+1
DOUT
b
DOUT
b+1
NOTE: The WRITE command may be to either bank, and the READ command may
be to either bank. DQM is LOW. CAS latency = 2 for illustration.
bank (provided that auto precharge was not activated),
and a full-page WRITE burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued tWR after the
clock edge at which the last desired input data element is
registered. The two-clock WRITE recovery version (A2)
requires at least two clocks, regardless of frequency, as
well as tWR being met. In addition, when truncating a
WRITE burst, the DQM signal must be used to mask
input data for the clock edge on which the PRECHARGE
command is entered. An example is shown in Figure 18.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the op-
timum time (as described above) provides the same op-
eration that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
Figure 18
WRITE to PRECHARGE
T0
T1
T2
T3
CLK
T4
T5
T6
tWR@ tCK 15ns
DQM
COMMAND
WRITE
t RP
NOP
PRECHARGE
NOP
NOP
ACTIVE
NOP
ADDRESS
DQ
BANK a,
COL n
DIN
n
BANK
(a or all)
DIN
n+1
t WR
BANK a,
ROW
tWR@ tCK < 15ns
DQM
COMMAND
WRITE
NOP
ADDRESS
BANK a,
COL n
DQ
DIN
n
DIN
n+1
t RP
NOP
PRECHARGE
NOP
NOP
BANK
(a or all)
t WR
ACTIVE
BANK a,
ROW
NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length
of two.
DON’T CARE
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
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