MT48LC4M8A1TG-10 View Datasheet(PDF) - Micron Technology
Part Name
Description
View to exact match
MT48LC4M8A1TG-10 Datasheet PDF : 50 Pages
| |||
READs
READ bursts are initiated with a READ command, as
shown in Figure 5 (A9 is a “Don’t Care”on x8).
The starting column and bank addresses are pro-
vided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric READ commands used in the following illustra-
tions, auto precharge is disabled.
During READ bursts, the valid data-out element from
the starting column address will be available following
the CAS latency after the READ command. Each subse-
quent data-out element will be valid by the next positive
clock edge. Figure 6 shows general timing for each pos-
sible CAS latency setting.
Figure 5
READ Command
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0-A9
COLUMN
ADDRESS
(A9 is a “Don’t Care” for x8)
A10
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK 1
BA
BANK 0
16 MEG: x4, x8
SDRAM
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go High-Z. A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to column 0 and continue.)
A fixed-length READ burst may be followed by, or
truncated with, a READ burst (provided that auto
precharge is not activated), and a full-page READ burst
can be truncated with a subsequent READ burst. In either
case, a continuous flow of data can be maintained. The
first data element from the new burst follows either the
last element of a completed burst or the last desired data
element of a longer burst that is being truncated. The
new READ command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
Figure 6
CAS Latency
T0
T1
T2
CLK
COMMAND
DQ
READ
tLZ
tAC
NOP
tOH
DOUT
CAS Latency = 1
T0
T1
T2
T3
CLK
COMMAND
DQ
READ
NOP
tLZ
tAC
CAS Latency = 2
NOP
tOH
DOUT
CLK
COMMAND
T0
READ
DQ
T1
T2
NOP
NOP
tLZ
tAC
CAS Latency = 3
T3
T4
NOP
tOH
DOUT
DON’T CARE
UNDEFINED
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
Share Link: 