CY7C4221V-25JC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
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CY7C4221V-25JC Datasheet PDF : 16 Pages
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1CY 7C42 31 V/4 24 1V
/4 25 1V
fax id: 5418
CY7C4421V/4201V/4211V/4221V
PRELIMINARY CY7C4231V/4241V/4251V
Low Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Features
• High-speed, low-power, first-in, first-out (FIFO)
memories
• 64 x 9 (CY7C4421V)
• 256 x 9 (CY7C4201V)
• 512 x 9 (CY7C4211V)
• 1K x 9 (CY7C4221V)
• 2K x 9 (CY7C4231V)
• 4K x 9 (CY7C4241V)
• 8K x 9 (CY7C4251V)
• High-speed 66-MHz operation (15 ns read/write cycle
time)
• Low power (ICC = 20 mA)
• 3.3V operation for low power consumption and easy
integration into low voltage systems
• 5V tolerant inputs VIH max= 5V
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, and Programmable Almost Empty and
Almost Full status flags
• TTL compatible
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Width Expansion Capability
• Space saving 32-pin 7mm x 7mm TQFP
• 32-pin PLCC
Functional Description
The CY7C42X1V are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
are 9 bits wide. Programmable features include Almost
Full/Almost Empty flags. These FIFOs provide solutions for a
wide variety of data buffering needs, including high-speed
data acquisition, multiprocessor interfaces, and communica-
tions buffering.
These FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and two write-en-
able pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and
two read-enable pins (REN1, REN2). In addition, the
CY7C42X1V has an output enable pin (OE). The read (RCLK)
and write (WCLK) clocks may be tied together for single-clock
operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up
to 66 MHz are achievable.
Depth expansion is possible using one enable input for sys-
tem control, while the other enable is controlled by expansion
logic to direct the flow of data
.
Logic Block Diagram
WCLK WEN1 WEN2/LD
WRITE
CONTROL
WRITE
POINTER
RS
RESET
LOGIC
D0 − 8
INPUT
REGISTER
Dual Port
RAM Array
64 x 9
8k x 9
THREE-STATE
OUTPUTREGISTER
OE
Q0 − 8
Pin Configuration
PLCC
Top View
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
READ
POINTER
EF
PAE
PAF
FF
READ
CONTROL
RCLK REN1 REN2
42X1V–1
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
4 3 2 1 323130
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 1516 17 1819 20
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
42X1V–2
TQFP
Top View
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
32 31 30 29 28 27 26 25
1
24
WEN1
2
23
WCLK
3
22
WEN2/LD
4
21
VCC
5
20
Q8
6
19
Q7
7
18
Q6
8
17
Q5
9 10 11 12 13 14 15 16
42X1V–3
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 1997 – Revised August 18, 1997
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