Table 4. Control 1
Address: 21h
Reset Value: 0010_1100
Type: Read/Write
BOLD is default state
Bit #
Name
Size (Bits)
7:5 Input Resistance
4:2
VLDO_OUT
000: 8 kΩ
001: 10 kΩ
010: 12 kΩ
3
011: 14 kΩ
100: 16 kΩ
101: 18 kΩ
110: 20 kΩ
111: 22 kΩ
000: 2.4 V
001: 2.6 V
010: 2.8 V
3
011: 3.0 V
100: 3.2 V
101 :3.4 V
110: 3.6 V
1:0
Reserved
2
Not used
Description
Table 5. Status
Address: 22h
Reset Value: 0000_1110
Type: Read Only
Bit #
Name
Size (Bits)
Description
7:4
Reserved
3
VDD_G
4
Not used
0: Input voltage is not valid (under UVLO); input voltage is less than 2.3 V
1
(rising) / 2.1 V (falling)
1: Input voltage is valid (over UVLO)
2 VLDO_OUT_G
0: Regulator output is not valid (VLDO_OUT is less than 70% of VLDO_OUT
1
programmed)
1: Regulator output is valid
1
OT
1
0: Over-temperature protection is tripped
1: Over-temperature protection is not tripped
0
Reserved
1
Not used, default is 0
Table 6. VDD vs. VLDO_OUT
2.7
2.4
VLDO_OUT
2.6
(Programmed Voltage)
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
3.0
2.4
2.6
2.8
9
VDD (V)
3.3
4.5
2.4
2.4
2.6
2.6
2.8
2.8
3.0
3.0
3.2
3.2
3.4
3.6
5.0
5.5
2.4
2.4
2.6
2.6
2.8
2.8
3.0
3.0
3.2
3.2
3.4
3.4
3.6
3.6
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