Applications Information
The FAH4830 has the external PWM input pin for the
motor driver block. In ERM Mode, the device uses the
39 nF external capacitor as an integrator. This converts
the PWM output to differential DC levels on the
MDP / MDN outputs.
In the LRA Mode, to control the 10 kHz to 50 kHz
frequency range of the PWM input signal; the device
incorporates an internal clock-dividing feature that can
be modified via the I2C register settings. This allows the
user flexibility to obtain the correct resonant frequency
for the chosen LRA device.
The input signal’s duty cycle changes the amplitude of
the positive and negative outputs for the motor drive.
The LRA and ERM motor vibration strength depends on
the PWM duty cycle. When the duty cycle is 50/50, the
device stops. The vibration is maximum when the duty
ratio is 1% to 99% or 99% to 1%. The regulator voltage
level controls the amplitude of the signal at the motor.
Figure 9. LRA Motor Drive (MDN, MDP)
Figure 10. System Block Diagram
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
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