FAH4830 View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
View to exact match
FAH4830
Fairchild Semiconductor
FAH4830 Datasheet PDF : 15 Pages
| |||
Functional Description
I2C Control
Writing to and reading from registers is accomplished
via the I2C interface. The I2C protocol requires that one
device on the bus initiates and controls all read and
write operations. This device is called the “master”
device. The master device generates the SCL signal,
which is the clock signal for all other devices on the bus.
All other devices on the bus are called “slave” devices.
The FAH4830 is a slave device. Both the master and
slave devices can send and receive data on the bus.
During I2C operations, one data bit is transmitted per
clock cycle. All I2C operations follow a repeating nine-
clock-cycle pattern that consists of eight bits (one byte)
of transmitted data followed by an acknowledge (ACK)
or not acknowledge (NACK) from the receiving device.
Note that there are no unused clock cycles during any
operation; therefore, there must be no breaks in the
stream of data and ACKs/NACKs during data transfers.
For most operations, I2C protocol requires the SDA line
remain stable (unmoving) whenever SCL is HIGH. For
example, transitions on the SDA line can only occur
when SCL is LOW. The exceptions are when the master
device issues a START or STOP condition. The slave
device cannot issue a START or STOP condition.
START Condition: This condition occurs when the SDA
line transitions from HIGH to LOW while SCL is HIGH.
The master device uses this condition to indicate that a
data transfer is about to begin.
STOP Condition: This condition occurs when the SDA
line transitions from LOW to HIGH while SCL is HIGH.
The master device uses this condition to signal the end
of a data transfer.
Acknowledge and Not Acknowledge: When data is
transferred to the slave device, the slave device sends
acknowledge (ACK) after receiving every byte of data.
The receiving device sends an ACK by pulling SDA
LOW for one clock cycle.
When the master device is reading data from the slave
device, the master sends an ACK after receiving every
byte of data. Following the last byte, a master device
sends a “not acknowledge” (NACK) instead of an ACK,
followed by a STOP condition. A NACK is indicated by
leaving SDA HIGH during the clock after the last byte.
Slave Address
Each slave device on the bus must have a unique
address so the master can identify which device is
sending or receiving data. The FAH4830 slave address
is 0000110X binary, where “X” is the read/write bit.
Master write operations are indicated when X = 0.
Master read operations are indicated when X = 1.
Writing to and Reading from the FAH4830
All read and write operations must begin with a START
condition generated by the master. After the START
condition, the master must immediately send a slave
address (7 bits), followed by a read/write bit. If the slave
address matches the address of the FAH4830, the
FAH4830 sends an ACK after receiving the read/write
bit by pulling the SDA line LOW for one clock cycle.
Setting the Pointer
For all operations, a “pointer” stored in the command
register must be indicating the register to be written or
read. To change the pointer value in the command
register, the read/write bit following the address must be
0. This indicates that the master writes new information
into the command register.
After the FAH4830 sends an ACK in response to
receiving the address and read/write bit, the master
must transmit an appropriate 8-bit pointer value, as
explained in the I2C Registers section. The FAH4830
sends an ACK after receiving the new pointer data.
The pointer-set operation is illustrated in Figure 7 and
Figure 8. Any time a pointer-set is performed, it must be
immediately followed by a read or write operation. The
command register retains the pointer between
operations; once a register is indicated, subsequent
read operations do not require a pointer set cycle. Write
operations always require the pointer be reset.
Reading
If the pointer is already pointing to the desired register,
the master can read from that register by setting the
read/write bit (following the slave address) to 1. After
sending an ACK, data transmission begins during the
following clock cycle. The master should respond with a
NACK, followed by a STOP condition (see Figure 5).
The master can read multiple bytes by responding to the
data with an ACK instead of a NACK and continuing to
send SCL pulses, as shown in Figure 6. The FAH4830
increments the pointer by one and sends the data from
the next register. The master indicates the last data byte
by responding with a NACK, followed by a STOP.
To read from a register other than the one currently
indicated by the command register, a pointer to the
desired register must be set. Immediately following the
pointer-set, the master must perform a REPEAT START
condition (see Figure 8), which indicates to the
FAH4830 that a new operation is about to occur. If the
REPEAT START condition does not occur, the
FAH4830 assumes that a write is taking place and the
selected register is overwritten by the upcoming data on
the data bus. After the START condition, the master
must again send the device address and read/write bit.
This time, the read/write bit must be set to 1 to indicate
a read. The rest of the read cycle is the same as
described for reading from a preset pointer location.
Writing
All writes must be preceded by a pointer set, even if the
pointer is already pointing to the desired register.
Immediately following the pointer-set, the master must
begin transmitting the data to be written. After
transmitting each byte of data, the master must release
the Serial Data (SDA) line for one clock cycle to allow
the FAH4830 to acknowledge receiving the byte. The
write operation should be terminated by a STOP
condition from the master (see Figure 7).
As with reading, the master can write multiple bytes by
continuing to send data. The FAH4830 increments the
pointer by one and accepts data for the next register.
The master indicates the last data byte by issuing a
STOP condition.
© 2012 Fairchild Semiconductor Corporation
FAH4830 • 1.0.1
6
www.fairchildsemi.com
Share Link: