AD7606(2017) View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
AD7606
(Rev.:2017)
(Rev.:2017)
Analog Devices
AD7606 Datasheet PDF : 36 Pages
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Data Sheet
AD7606/AD7606-6/AD7606-4
Parameter
t27
t28
t29
Limit at TMIN, TMAX
(0.1 × VDRIVE and
0.9 × VDRIVE
Logic Input Levels)
Min Typ Max
19
24
17
22
24
Limit at TMIN, TMAX
(0.3 × VDRIVE and
0.7 × VDRIVE
Logic Input Levels)
Min Typ Max
Unit
22 ns
29 ns
20 ns
27 ns
29 ns
Description
Delay from RD falling edge to FRSTDATA low
VDRIVE = 3.3 V to 5.25V
VDRIVE = 2.3 V to 2.7V
Delay from 16th SCLK falling edge to FRSTDATA low
VDRIVE = 3.3 V to 5.25V
VDRIVE = 2.3 V to 2.7V
Delay from CS rising edge until FRSTDATA three-
state enabled
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2 In oversampling mode, typical tCONV for the AD7606-6 and AD7606-4 can be calculated using ((N × tCONV) + ((N − 1) × 1 µs)). N is the oversampling ratio. For the AD7606-6,
tCONV = 3 µs; and for the AD7606-4, tCONV = 2 µs.
3 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets.
4 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
Timing Diagrams
CONVST A,
CONVST B
CONVST A,
CONVST B
BUSY
CS
RESET
t5
t1
t7
tRESET
tCYCLE
t3
tCONV
t2
t4
Figure 2. CONVST Timing—Reading After a Conversion
t5
CONVST A,
CONVST B
CONVST A,
CONVST B
tCYCLE
t2
t3
tCONV
t1
BUSY
t6
CS
RESET
t7
tRESET
Figure 3. CONVST Timing—Reading During a Conversion
Rev. D | Page 9 of 36
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