AD7606(2017) View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
AD7606
(Rev.:2017)
(Rev.:2017)
Analog Devices
AD7606 Datasheet PDF : 36 Pages
| |||
Data Sheet
AD7606/AD7606-6/AD7606-4
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter
PARALLEL/SERIAL/BYTE MODE
tCYCLE
t2
CONV
tWAKE-UP STANDBY
tWAKE-UP SHUTDOWN
Internal Reference
External Reference
tRESET
tOS_SETUP
tOS_HOLD
t1
t2
t3
t4
t5 3
t6
t7
PARALLEL/BYTE READ
OPERATION
t8
t9
t10
t11
t12
Limit at TMIN, TMAX
(0.1 × VDRIVE and
0.9 × VDRIVE
Logic Input Levels)
Min Typ Max
5
9.7
3.45 4
4.15
3
2
7.87
9.1
16.05
18.8
33
39
66
78
133
158
257
315
100
30
13
50
20
20
40
25
25
0
0.5
25
25
0
0
16
21
25
32
15
22
Limit at TMIN, TMAX
(0.3 × VDRIVE and
0.7 × VDRIVE
Logic Input Levels)
Min Typ Max
Unit
Description
3.45 4
3
2
7.87
16.05
33
66
133
257
5
µs
9.4 µs
10.7 µs
4.15 µs
µs
µs
9.1 µs
18.8 µs
39 µs
78 µs
158 µs
315 µs
100 µs
1/throughput rate
Parallel mode, reading during or after conversion; or
serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a
conversion using DOUTA and DOUTB lines
Serial mode reading after a conversion; VDRIVE = 2.7 V
Serial mode reading after a conversion; VDRIVE = 2.3 V,
DOUTA and DOUTB lines
Conversion time
Oversampling off; AD7606
Oversampling off; AD7606-6
Oversampling off; AD7606-4
Oversampling by 2; AD7606
Oversampling by 4; AD7606
Oversampling by 8; AD7606
Oversampling by 16; AD7606
Oversampling by 32; AD7606
Oversampling by 64; AD7606
STBY rising edge to CONVST x rising edge; power-up
time from standby mode
30 ms STBY rising edge to CONVST x rising edge; power-up
time from shutdown mode
13 ms STBY rising edge to CONVST x rising edge; power-up
time from shutdown mode
50
ns RESET high pulse width
20
ns BUSY to OS x pin setup time
20
ns BUSY to OS x pin hold time
45 ns CONVST x high to BUSY high
25
ns Minimum CONVST x low pulse
25
ns Minimum CONVST x high pulse
0
ns BUSY falling edge to CS falling edge setup time
0.5 ms
Maximum delay allowed between CONVST A, CONVST
B rising edges
25 ns
Maximum time between last CS rising edge and BUSY
falling edge
25
ns Minimum delay between RESET low to CONVST x high
0
ns CS to RD setup time
0
ns CS to RD hold time
RD low pulse width
19
ns
VDRIVE above 4.75 V
24
ns
VDRIVE above 3.3 V
30
ns
VDRIVE above 2.7 V
37
ns
VDRIVE above 2.3 V
15
ns RD high pulse width
22
ns CS high pulse width (see Figure 5); CS and RD linked
Rev. D | Page 7 of 36
Share Link: