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AD7606(2017) View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
AD7606
(Rev.:2017)
8-/6-/4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC
ADI
Analog Devices ADI
AD7606 Datasheet PDF : 36 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD7606/AD7606-6/AD7606-4
Data Sheet
Parameter
t13
t144
t15
t16
t17
SERIAL READ OPERATION
fSCLK
t18
t19 4
t20
t21
t22
t23
FRSTDATA OPERATION
t24
t25
t26
Limit at TMIN, TMAX
(0.1 × VDRIVE and
0.9 × VDRIVE
Logic Input Levels)
Min Typ Max
16
20
25
30
16
21
25
32
6
6
22
Limit at TMIN, TMAX
(0.3 × VDRIVE and
0.7 × VDRIVE
Logic Input Levels)
Min Typ Max
Unit
19 ns
24 ns
30 ns
37 ns
19 ns
24 ns
30 ns
37 ns
6
ns
6
ns
22 ns
Description
Delay from CS until DB[15:0] three-state disabled
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Data access time after RD falling edge
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
Data hold time after RD falling edge
CS to DB[15:0] hold time
Delay from CS rising edge to DB[15:0] three-state
enabled
0.4 tSCLK
0.4 tSCLK
7
23.5
17
14.5
11.5
15
20
30
17
23
27
34
0.4 tSCLK
0.4 tSCLK
7
22
Frequency of serial read clock
20 MHz VDRIVE above 4.75 V
15 MHz VDRIVE above 3.3 V
12.5 MHz VDRIVE above 2.7 V
10 MHz VDRIVE above 2.3 V
Delay from CS until DOUTA/DOUTB three-state
disabled/delay from CS until MSB valid
18 ns
23 ns
35 ns
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE = 2.3 V to 2.7 V
Data access time after SCLK rising edge
20 ns
26 ns
32 ns
39 ns
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
ns SCLK low pulse width
ns SCLK high pulse width
SCLK rising edge to DOUTA/DOUTB valid hold time
22 ns
CS rising edge to DOUTA/DOUTB three-state enabled
Delay from CS falling edge until FRSTDATA three-
state disabled
15
18 ns
VDRIVE above 4.75 V
20
23 ns
VDRIVE above 3.3 V
25
30 ns
VDRIVE above 2.7 V
30
35 ns
VDRIVE above 2.3 V
ns
Delay from CS falling edge until FRSTDATA high,
serial mode
15
18 ns
VDRIVE above 4.75 V
20
23 ns
VDRIVE above 3.3 V
25
30 ns
VDRIVE above 2.7 V
30
35 ns
VDRIVE above 2.3 V
Delay from RD falling edge to FRSTDATA high
16
19 ns
VDRIVE above 4.75 V
20
23 ns
VDRIVE above 3.3 V
25
30 ns
VDRIVE above 2.7 V
30
35 ns
VDRIVE above 2.3 V
Rev. D | Page 8 of 36

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