IDT72510L25J View Datasheet(PDF) - Integrated Device Technology
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Description
View to exact match
IDT72510L25J
Integrated Device Technology
IDT72510L25J Datasheet PDF : 32 Pages
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IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V±10%, TA = 0°C to +70°C)
Symbol
Parameter
IDT72510L25
IDT72520L25
Min.
Max.
PORT B RETRANSMIT and PARITY TIMING
tbDSBH
RER , REW, LDRER,
LDREW set-up and
recovery time
10
—
tbPER
Parity error time
20
—
BYPASS TIMING
tBYA
Bypass access time
—
15
tBYD
Bypass delay
—
10
taBYDV Bypass data valid time
15
—
from DSA
tbBYDV (3) Bypass data valid time
3
—
from DSB
FLAG TIMING
tREF
Read clock edge to
Empty Flag asserted
—
25
tWEF
Write clock edge to
—
25
Empty Flag not asserted
tRFF
Read clock edge to Full
—
25
Flag not asserted
tWFF
Write clock edge to Full
—
25
Flag asserted
tRAEF
Read clock edge to
Almost-Empty Flag
asserted
—
40
tWAEF
Write clock edge to
—
40
Almost-Empty Flag not
asserted
tRAFF
Read clock edge to
Almost-Full Flag not
asserted
—
40
tWAFF
Write clock edge to
Almost-Full Flag
asserted
—
40
Commercial
IDT72510L35
IDT72520L35
Min.
Max.
10
—
25
—
—
20
—
15
15
—
3
—
—
35
—
35
—
35
—
35
—
50
—
50
—
50
—
50
IDT72510L50
IDT72520L50
Min.
Max. Unit
15
—
ns
Timing
Figure
9, 18
30
—
ns
19
—
30
ns
16
—
20
ns
16
15
—
ns
16
3
—
ns
16
—
45
ns 14, 15, 20, 22
—
45
ns 14, 15, 20, 22
—
45
ns 14, 15, 21, 23
—
45
ns 14, 15, 21, 23
—
60
ns
20, 22
—
60
ns
20, 22
—
60
ns
21, 23
—
60
ns
21, 23
NOTES:
1. Read and Write are internal signals derived fromDSA , R/WA , DSB, R/WB, RB, and WB.
2669 tbl 25
2. Although the flags, Empty, Almost-Empty, Almost-Full, and Full Flags are internal flags, the timing given is for those assigned to external pins.
3. Values guaranteed by design, not currently tested.
5.31
20
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