IDT72510L25J View Datasheet(PDF) - Integrated Device Technology

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IDT72510L25J

BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT – 1024 x 9-BIT 1024 x 18-BIT – 2048 x 9-BIT

Integrated Device Technology 

IDT72510, IDT72520

BUS MATCHING BIDIRECTIONAL FIFO

COMMERCIAL TEMPERATURE RANGE

two parity error bits is brought out to FLGA pin by setting Bit 11

of Configuration Register 7.

Parity generation creates the ninth bit. This ninth bit is

placed on DB8 for A->B read operation, and on DA16 or RAM

array for B->A write operation.

It is recommended that if the parity pins (DB8, DA16, and DA17)

are not used, they should be pulled down with 10K resistors

for noise immunity.

Intelligent Reread/Rewrite

Intelligent reread/rewrite is a method the BiFIFO uses to

help assure data integrity. Port B of the BiFIFO has two extra

pointers, the Reread Pointer and the Rewrite Pointer. The

Reread Pointer is associated with the A->B FIFO Read

Pointer, while the Rewrite Pointer is associated with the B->A

FIFO Write Pointer. The Reread Pointer holds the start ad-

dress of a data block in the A->B FIFO RAM, and the Read

Pointer is the current address of the same FIFO RAM array.

By loading the Read Pointer with the value held in the Reread

Pointer (RER asserted), reads will start over at the beginning

of the data block. In order to mark the beginning of a data

block, the Reread Pointer should be loaded with the Read

Pointer value (LDRER asserted) before the first read is

performed on this data block. Figure 6 shows a Reread

operation.

Similarly, the Rewrite Pointer holds the start address of a

data block in the B->A FIFO RAM, while the Write Pointer is

the current address within the RAM array. The operation of the

REW and LDREW is identical to the RER and LDRER dis-

cussed above. Figure 7 shows a Rewrite operation.

For the reread data protection, Bit 2 of Configuration

Register 5 can be set to 1 to prevent the data block form being

overwritten. In this way, the assertion of A->B full flag will occur

when the write pointer meets the reread pointer instead of the

read pointer as in the normal definition. For the rewrite data

protection, Bit 3 of Configuration Register 5 can be set to 1 to

prevent the data block from being read. In this case, the

assertion of B->A empty flag will occur when the read pointer

meets the rewrite pointer instead of the write pointer.

In conclusion, Bit 2 and 3 of Configuration Register 5 are

used to redefine Full & Empty flags for data block partition.

Although it can serve the purpose of data protection, the

setting of these 2 bits is independent of the functions caused

by RER/REW, or LDRER/LDREW assertions.

REREAD OPERATIONS (1,2)

Reread

Pointer

Reread

function

REWRITE OPERATIONS (3,4)

Read

Pointer

Write

Pointer

A→B

FIFO

NOTES:

1. If bit 2 is set to 1,

Empty flag asserted if Read = Write

Full flag asserted if Reread + FIFO size = Write

2. If bit 2 is set to 0,

Empty flag asserted if Read = Write

Full flag asserted if Read + FIFO size = Write

Write

Pointer

B→A

FIFO

Load

Reread

function

Load Rewrite

function

Read

Pointer

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Rewrite

function

Rewrite

Pointer

NOTES:

1. If bit 3 is set to 1,

Empty flag asserted if Read = Rewrite

Full flag asserted if Read + FIFO size = Write

2. If bit 3 is set to 0,

Empty flag asserted if Read = Write

Full flag asserted if Read + FIFO size = Write

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Figure 6. BiFIFO Reread Operations

Figure 7. BiFIFO Rewrite Operations

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