IDT72510L25J View Datasheet(PDF) - Integrated Device Technology
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IDT72510L25J
Integrated Device Technology
IDT72510L25J Datasheet PDF : 32 Pages
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IDT72510, IDT72520
BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
Status Register
The Status Register reports the state of the programmable
flags, the DMA read/write direction, the Odd Byte Register
valid bit, and parity errors. The Status Register is read by
setting CSA = 0, A1 = 1, A0 = 1 (see Table 1).
There are two Status Register formats that are set by a
Status Register format command. Format 0 stores the Odd
Byte Register data in the lower eight bits of the Status
Register, while format 1 reports the flag states and the DMA
read/write direction in the lower eight bits. The upper eight bits
are identical for both formats. The flag states, the parity errors,
the Odd Byte Register valid bit, and the Status Register format
are all in the upper eight bits of the Status Register. See Table
8 for both Status Register formats.
Configuration Registers
The eight Configuration Register formats are shown in
Table 9. Configuration Registers 0-3 contain the program-
mable flag offsets for the Almost Empty and Almost Full flags.
These offsets are set to 0 when a hardware reset or a software
reset all is applied. Note that Table 9 shows that Configuration
Registers 0-3 are 10 bits wide to accommodate the 1024
locations in each FIFO memory of the IDT72520. Only 9 least
significant bits are used for the 512 locations of the IDT72510;
the most significant bit, bit 9, must be set to 0.
Configuration Register 4 is used to assign the internal flags
to the external flag pins (FLGA-FLGD). Each external flag pin
is assigned an internal flag based on the four bit codes shown
in Table 10. The default condition for Configuration Register
4 is 6420H as shown in Table 7. The default flag assignments
are: FLGD is assigned B→A Full, FLGC is assigned B→A Empty,
FLGB is assigned A→B Full, FLGA is assigned A→B Empty.
Configuration Register 5 is a general control register. The
format of Configuration Register 5 is shown in Table 11. Bit 0
sets the Intel-style interface (RB, WB) or Motorola-style inter-
face (DSB, R/WB) for Port B. Bit 1 changes the byte order for
data coming through Port B. Bits 2 and 3 redefine Full and
Empty Flags for reread/rewrite data protection.
Bits 4-9 control the DMA interface and are only applicable
in peripheral interface mode. In processor interface mode,
these bits are don’t care states. Bits 4 and 5 set the polarity
of the DMA control pins REQ and ACK, respectively. An
internal clock controls all DMA operations. This internal clock
is derived from the external clock (CLK). Bit 9 determines the
internal clock frequency: the internal clock = CLK or the
internal clock = CLK divided by 2. Bit 8 sets whether RB, WB,
and DSB are asserted for either one or two internal clocks. Bits
6 and 7 set the number of internal clocks between REQ
assertion and ACK assertion. The timing can be from 2 to 5
cycles as shown in Figure 17.
Bit 10 controls Port B processor or peripheral interface
mode. In processor mode, the Port B control pins (RB, WB, DSB,
R/WB) are inputs and the DMA controls are ignored. In
peripheral mode, the Port B control pins are outputs and the
DMA controls are active.
Bits 11 and 12 set the width expansion mode. For 18- to
9-bit configurations or 36- to 18-bit configurations, the BiFIFO
should be set in stand-alone mode. For a 36- to 9-bit
configuration, one BiFIFO must be in slave mode and the
other BiFIFO must be in master mode. The master BiFIFO
allows the first two bytes transferred across Port B to go to the
slave BiFIFO, then the next two bytes go to the master BiFIFO.
Configuration Register 7 controls the parity functions of
Port B as shown in Table 12. Either parity generation or parity
STATUS REGISTER FORMAT 0
STATUS REGISTER FORMAT 1
Bit
Signal
0
1
2
3
Odd Byte Register
4
Bit
Signal
0
Reserved
1
Reserved
2
Reserved
3
DMA Direction
4
A→B Empty Flag
5
6
7
8
Valid Bit
9
Write Parity Error
10
Read Parity Error
11
Status Register Format = 0
5
A→B Almost-Empty Flag
6
B→A Full Flag
7
B→A Almost-Full Flag
8
Valid Bit
9
Write Parity Error
10
Read Parity Error
11
Status Register Format = 1
12
A→B Full Flag
12
A→B Full Flag
13
A→B Almost-Full Flag
13
A→B Almost-Full Flag
14
B→A Empty Flag
14
B→A Empty Flag
15
B→A Almost-Empty Flag
2669 tbl 11
15
B→A Almost-Empty Flag
Table 8. The Two Status Register Formats
2669 tbl 12
5.31
12
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