VV5409C001 View Datasheet(PDF) - Vision
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VV5409C001 Datasheet PDF : 39 Pages
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VV5409 CMOS Monochrome Sensor Datasheet (Restricted) Rev 1.0
then the serial interface communications by Video Processor will not be acknowledged.
3. Poll for 32 consecutive FH values on the data bus, if this condition is satisfied then the sensor is
present. The Video processor should set the camera_present flag.
4. Initiate the Auto-load daisy-chain to read setup data and the defect data from the appropriate serial
CMOS E2PROMs into the sensor and co-processor as a appropriate (only where a VISION coo-proc-
essor is used).
5. Disable the sensor clock CKI.
6. The Video Processor should generate the VP_Ready interrupt.
7. Once the host software serviced the VP_Ready interrupt, then the sensor and video processor is ready
to generate video data.
8. To enable video data, the host software, sets the low-power mode bit low. The video processor must
enable CLKI at least 16 CLKI clock cycles before issuing the “Exit Low-Power Mode” command via the
serial interface.
After the “Exit Low-Power Mode” command has been sent the sensor will output for one frame, a continuous
stream of alternating 9 H and 6 H values on D[3:0]. By locking onto the resulting 0101/1010 patterns
appearing on the data bus lines the video processor can determine the best sampling position for the nibble
data. After the last 9 H 6 H pair has been output the data bus returns to F H until the start of fifth frame after
CKI has been enabled when the first active frame output. After the video processor has determined the
correct sampling position for the data, it should then wait for the next start of frame line (SOF).
If the video processor detects 32 consecutive 0H values on the data bus, then the sensor has been removed.
The sensor clock, CKI, should be held low.
5.6.2 Low-Power Mode
Under the control of the serial-interface, the sensor’s analogue circuitry can be powered-down, and then
powered-up. When the low-power bit is set through the serial-interface, all the data-bus lines will go high at
the end of the current frame’s, end-of-frame line. At this point the analogue circuits in the sensor, will power-
down. The system clock must remain active for the duration of low power mode.
Only the analogue circuits are powered-down, the values of the serial-interface registers e.g. exposure, and
gain are preserved.
The internal frame timing is reset to the start of a video frame, on exiting low-power mode.
In a similar manner to the previous section, the first frame after the serial comms contains a continuous
stream of alternating 9 H and 6 H to allow the video processor to re-confirm its sampling position. Then three
frames later the first start-of-frame line is generated.
5.6.3 Sleep Mode
Sleep mode is similar to the low-power mode, except that the analogue circuitry remains powered. When the
sleep command is received through the serial-interface, the pixel-array will be put into reset, and all the data-
lines will go high at the end of the current frame. Again the system clock must remain active for the duration
of the sleep mode.
When the sleep mode is disabled, the CMOS sensor’s frame timing, is reset to the start of a frame. During
the first frame, after exiting from the sleep mode, the data-bus will remain high, while the exposure value
propagates through the pixel-array. At the start of the second frame, the first start-of-field line will be
generated.
5.6.4 Application of the system clock during sensor low-power modes
For successfully entry and exit into and out of low power and ‘sleep’ modes the system clock, CLKI, must
remain active for the duration of these modes.
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VV5409 CMOS Monochrome Sensor Datasheet (Restricted) Rev 1.0
5.7 Qualification of Output Data
There are two distinct ways for qualifying the data nibbles appearing of the output data bus
5.7.1 Using the External Clock signal applied to CLKI
The data on the output data bus, changes on the rising edge of CLKI. The delay between the video processor
supplying a rising clock edge and the data on the data bus becoming valid, depends on the length of the cable
between the sensor and the video processor. To allow the video processor to find the best sampling position
for the data nibbles, via the serial interface the data bus can be forced to output continuously 9H, 6H, 9H, 6H,...
5.7.2 Data Qualification Clock, QCK
VV5409 provides a data qualification clock for the output bus There are two frequencies for the qualification
clock: one runs at the nibble rate and the other at the pixel read-out rate. The falling edge of the fast QCK
qualifies every nibble irrespective of whether it is most or least significant nibble. For the slow QCK, the rising
edge qualifies the most significant nibbles in the output data stream and the falling edge qualifies the least
significant nibbles in the output data stream.
There are 4 modes of operation of QCK.
1. Disabled (Always low - (Default)
2. Free running - qualifies the whole of the output data stream.
3. Embedded control sequences, status data and pixel data.
4. Pixel Data Only.
The operating mode for QCK is set via the serial interface. The QCK output is tri-stated when OEB is high.In
one of the modes available via the serial interface the slow version of QCK will appear on the QCK pin while
the fast version of the same signal will appear on the FST pin.
In the case where the border rows and columns are disabled, there is simply no qualification pulse at that
point in time i.e. when pixels 0,1, 354 and 355 are normally output.
The QCK pin can also be configured to output the state of a serial interface register bit. This feature allows
the sensor to control external devices, e.g. stepper motors, shutter mechanisms. The configuration details
for QCK can be found in sections 5.5.7 and 5.5.8 of this document.
5.7.3 Line Start Signal, LST
There are 4 modes of operation for the LST pin programmable via the serial interface:
1. Disabled (Always Low- Default).
2. Free running - LST signal occurs once at the beginning of every line.
3. All lines except blanking lines are qualified by LST.
4. Only Black and Visible Lines are qualified by LST.
The LST is tri-stated when OEB is high.
5.7.4 Frame Start Signal, FST
There are 3 modes of operation for the FST pin programmable via the serial interface:
1. Disabled (Always Low- Default).
2. Frame start signal. The FST signal occurs once frame, is high for 356 pixel periods (712 system clock
periods) and qualifies the data in the start of frame line.
3. Synchronisation Output Pulse -SNO - Refer to Section 8. on Synchronising multiple cameras.
4. As the de-bounced switch input.
Note: The function of the SNO pin has not been verified.
The FST is tri-stated when OEB is high.
The FST pin can also be configured to output the state of a serial interface register bit. This feature allows
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